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Do not call abc9 if no outputs

This commit is contained in:
Eddie Hung 2019-06-12 10:18:44 -07:00
parent 14e870d4c4
commit 8bb67fa67c
1 changed files with 70 additions and 59 deletions
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31
passes/techmap/abc9.cc
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@ -414,6 +414,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
bool count_output = false;
for (auto port_name : module->ports) {
RTLIL::Wire *port_wire = module->wire(port_name);
log_assert(port_wire);
if (port_wire->port_output) {
count_output = true;
break;
}
}
log_push();
if (count_output)
{
design->selection_stack.emplace_back(false);
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
@ -425,6 +439,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
handle_loops(design);
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
// count_gates, GetSize(signal_list), count_input, count_output);
Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
#if 0
@ -462,13 +479,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
module->fixup_ports();
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
// count_gates, GetSize(signal_list), count_input, count_output);
log_push();
//if (count_output > 0)
{
log_header(design, "Executing ABC9.\n");
std::string buffer;
@ -753,10 +764,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
design->remove(mapped_mod);
}
//else
//{
// log("Don't call ABC as there is nothing to map.\n");
//}
else
{
log("Don't call ABC as there is nothing to map.\n");
}
if (cleanup)
{