mirror of https://github.com/YosysHQ/yosys.git
Do not call abc9 if no outputs
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@ -414,6 +414,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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}
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}
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}
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}
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bool count_output = false;
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for (auto port_name : module->ports) {
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RTLIL::Wire *port_wire = module->wire(port_name);
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log_assert(port_wire);
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if (port_wire->port_output) {
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count_output = true;
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break;
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}
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}
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log_push();
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if (count_output)
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{
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design->selection_stack.emplace_back(false);
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design->selection_stack.emplace_back(false);
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RTLIL::Selection& sel = design->selection_stack.back();
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RTLIL::Selection& sel = design->selection_stack.back();
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sel.select(module);
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sel.select(module);
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@ -425,6 +439,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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handle_loops(design);
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handle_loops(design);
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//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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// count_gates, GetSize(signal_list), count_input, count_output);
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Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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#if 0
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#if 0
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@ -462,13 +479,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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}
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}
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module->fixup_ports();
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module->fixup_ports();
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//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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// count_gates, GetSize(signal_list), count_input, count_output);
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log_push();
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//if (count_output > 0)
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{
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log_header(design, "Executing ABC9.\n");
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log_header(design, "Executing ABC9.\n");
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std::string buffer;
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std::string buffer;
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@ -753,10 +764,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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design->remove(mapped_mod);
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design->remove(mapped_mod);
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}
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}
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//else
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else
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//{
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{
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// log("Don't call ABC as there is nothing to map.\n");
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log("Don't call ABC as there is nothing to map.\n");
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//}
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}
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if (cleanup)
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if (cleanup)
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{
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{
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