mirror of https://github.com/YosysHQ/yosys.git
Improved performance in equiv_simple
This commit is contained in:
Clifford Wolf
parent
3cbfa3815e
commit
893fe87a33
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@ -163,6 +163,7 @@ public:
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virtual void freeze(int id);
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virtual bool eliminated(int idx);
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void assume(int id);
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void assume(int id, int context_id) { assume(OR(id, NOT(context_id))); }
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int bind(int id, bool auto_freeze = true);
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int bound(int id) const;
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@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
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struct EquivSimpleWorker
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{
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Module *module;
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const vector<Cell*> &equiv_cells;
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Cell *equiv_cell;
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SigMap &sigmap;
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@ -36,9 +37,11 @@ struct EquivSimpleWorker
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int max_seq;
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bool verbose;
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EquivSimpleWorker(Cell *equiv_cell, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose, bool model_undef) :
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module(equiv_cell->module), equiv_cell(equiv_cell), sigmap(sigmap),
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bit2driver(bit2driver), satgen(&ez, &sigmap), max_seq(max_seq), verbose(verbose)
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pool<pair<Cell*, int>> imported_cells_cache;
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EquivSimpleWorker(const vector<Cell*> &equiv_cells, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose, bool model_undef) :
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module(equiv_cells.front()->module), equiv_cells(equiv_cells), equiv_cell(nullptr),
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sigmap(sigmap), bit2driver(bit2driver), satgen(&ez, &sigmap), max_seq(max_seq), verbose(verbose)
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{
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satgen.model_undef = model_undef;
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}
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@ -84,10 +87,11 @@ struct EquivSimpleWorker
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if (input_bits != nullptr) input_bits->insert(bit);
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}
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bool run()
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bool run_cell()
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{
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
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int ez_context = ez.frozen_literal();
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if (satgen.model_undef)
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{
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@ -95,14 +99,14 @@ struct EquivSimpleWorker
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int ez_b = satgen.importDefSigBit(bit_b, max_seq+1);
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int ez_undef_a = satgen.importUndefSigBit(bit_a, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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ez.assume(ez.NOT(ez_undef_a));
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ez.assume(ez.XOR(ez_a, ez_b), ez_context);
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ez.assume(ez.NOT(ez_undef_a), ez_context);
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}
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else
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{
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importSigBit(bit_b, max_seq+1);
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ez.assume(ez.XOR(ez_a, ez_b));
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ez.assume(ez.XOR(ez_a, ez_b), ez_context);
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}
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pool<SigBit> seed_a = { bit_a };
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@ -155,9 +159,12 @@ struct EquivSimpleWorker
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GetSize(problem_cells), GetSize(short_cells_cone_a), GetSize(short_cells_cone_b),
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(GetSize(short_cells_cone_a) + GetSize(short_cells_cone_b)) - GetSize(problem_cells));
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for (auto cell : problem_cells)
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if (!satgen.importCell(cell, step+1))
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for (auto cell : problem_cells) {
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auto key = pair<Cell*, int>(cell, step+1);
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if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1))
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log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
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imported_cells_cache.insert(key);
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}
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if (satgen.model_undef) {
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for (auto bit : input_bits)
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@ -167,9 +174,10 @@ struct EquivSimpleWorker
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if (verbose)
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log(" Problem size at t=%d: %d literals, %d clauses\n", step, ez.numCnfVariables(), ez.numCnfClauses());
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if (!ez.solve()) {
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if (!ez.solve(ez_context)) {
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log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
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equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
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ez.assume(ez.NOT(ez_context));
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return true;
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}
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@ -215,8 +223,29 @@ struct EquivSimpleWorker
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if (!verbose)
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log(" failed.\n");
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ez.assume(ez.NOT(ez_context));
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return false;
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}
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int run()
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{
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if (GetSize(equiv_cells) > 1) {
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SigSpec sig;
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for (auto c : equiv_cells)
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sig.append(sigmap(c->getPort("\\Y")));
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log(" Grouping SAT models for %s:\n", log_signal(sig));
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}
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int counter = 0;
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for (auto c : equiv_cells) {
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equiv_cell = c;
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if (run_cell())
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counter++;
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}
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return counter;
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}
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};
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struct EquivSimplePass : public Pass {
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@ -235,13 +264,16 @@ struct EquivSimplePass : public Pass {
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log(" -undef\n");
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log(" enable modelling of undef states\n");
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log("\n");
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log(" -nogroup\n");
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log(" disabling grouping of $equiv cells by output wire\n");
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log("\n");
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log(" -seq <N>\n");
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log(" the max. number of time steps to be considered (default = 1)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool verbose = false, model_undef = false;
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bool verbose = false, model_undef = false, nogroup = false;
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int success_counter = 0;
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int max_seq = 1;
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@ -257,6 +289,10 @@ struct EquivSimplePass : public Pass {
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model_undef = true;
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continue;
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}
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if (args[argidx] == "-nogroup") {
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nogroup = true;
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continue;
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}
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if (args[argidx] == "-seq" && argidx+1 < args.size()) {
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max_seq = atoi(args[++argidx].c_str());
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continue;
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@ -271,19 +307,26 @@ struct EquivSimplePass : public Pass {
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for (auto module : design->selected_modules())
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{
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vector<pair<SigBit, Cell*>> unproven_equiv_cells;
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SigMap sigmap(module);
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dict<SigBit, Cell*> bit2driver;
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dict<SigBit, dict<SigBit, Cell*>> unproven_equiv_cells;
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int unproven_cells_counter = 0;
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B"))
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unproven_equiv_cells.push_back(pair<SigBit, Cell*>(cell->getPort("\\Y").to_single_sigbit(), cell));
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if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
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auto bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
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auto bit_group = bit;
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if (!nogroup && bit_group.wire)
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bit_group.offset = 0;
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unproven_equiv_cells[bit_group][bit] = cell;
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unproven_cells_counter++;
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}
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if (unproven_equiv_cells.empty())
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continue;
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log("Found %d unproven $equiv cells in %s:\n", GetSize(unproven_equiv_cells), log_id(module));
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SigMap sigmap(module);
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dict<SigBit, Cell*> bit2driver;
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log("Found %d unproven $equiv cells (%d groups) in %s:\n",
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unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
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for (auto cell : module->cells()) {
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if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_"))
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@ -294,11 +337,17 @@ struct EquivSimplePass : public Pass {
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bit2driver[bit] = cell;
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}
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std::sort(unproven_equiv_cells.begin(), unproven_equiv_cells.end());
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for (auto it : unproven_equiv_cells) {
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EquivSimpleWorker worker(it.second, sigmap, bit2driver, max_seq, verbose, model_undef);
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if (worker.run())
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success_counter++;
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unproven_equiv_cells.sort();
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for (auto it : unproven_equiv_cells)
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{
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it.second.sort();
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vector<Cell*> cells;
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for (auto it2 : it.second)
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cells.push_back(it2.second);
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EquivSimpleWorker worker(cells, sigmap, bit2driver, max_seq, verbose, model_undef);
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success_counter += worker.run();
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}
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}
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