mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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@ -645,19 +645,12 @@ struct XAigerWriter
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// write_o_buffer(0);
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if (!box_list.empty() || !ff_bits.empty()) {
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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dict<IdString, Cell*> cell_cache;
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int box_count = 0;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = module->design->module(cell->type);
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
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RTLIL::Module* box_module = module->design->module(derived_name);
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if (box_module->has_processes())
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Pass::call_on_module(module->design, box_module, "proc");
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int box_inputs = 0, box_outputs = 0;
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// NB: Assume box_module->ports are sorted alphabetically
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@ -714,6 +707,9 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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module->design->selection_stack.emplace_back(false);
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module->design->selection().select(holes_module);
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