mirror of https://github.com/YosysHQ/yosys.git
Fixed opt_clean performance bug
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parent
853e949c0e
commit
8805c24640
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@ -33,53 +33,53 @@ using RTLIL::id2cstr;
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CellTypes ct, ct_reg, ct_all;
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CellTypes ct, ct_reg, ct_all;
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int count_rm_cells, count_rm_wires;
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int count_rm_cells, count_rm_wires;
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void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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void rmunused_module_cells(Module *module, bool verbose)
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{
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{
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SigMap sigmap(module);
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SigMap sigmap(module);
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
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pool<Cell*> queue, unused;
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dict<SigBit, pool<Cell*>> wire2driver;
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SigSet<RTLIL::Cell*> wire2driver;
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for (auto &it : module->cells_) {
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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for (auto &it2 : cell->connections()) {
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if (!ct.cell_input(cell->type, it2.first))
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if (!ct.cell_input(cell->type, it2.first))
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wire2driver.insert(sigmap(it2.second), cell);
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for (auto bit : sigmap(it2.second))
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if (bit.wire != nullptr)
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wire2driver[bit].insert(cell);
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}
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}
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if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
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if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
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queue.insert(cell);
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queue.insert(cell);
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else
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unused.insert(cell);
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unused.insert(cell);
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}
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}
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for (auto &it : module->wires_) {
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for (auto &it : module->wires_) {
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RTLIL::Wire *wire = it.second;
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Wire *wire = it.second;
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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pool<RTLIL::Cell*> cell_list;
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for (auto bit : sigmap(wire))
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wire2driver.find(sigmap(wire), cell_list);
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for (auto c : wire2driver[bit])
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for (auto cell : cell_list)
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queue.insert(c), unused.erase(c);
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queue.insert(cell);
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}
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}
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}
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}
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while (!queue.empty())
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while (!queue.empty())
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{
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{
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
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pool<SigBit> bits;
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for (auto cell : queue)
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for (auto cell : queue)
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unused.erase(cell);
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for (auto &it : cell->connections())
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for (auto cell : queue) {
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if (!ct.cell_output(cell->type, it.first))
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for (auto &it : cell->connections()) {
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for (auto bit : sigmap(it.second))
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if (!ct.cell_output(cell->type, it.first)) {
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bits.insert(bit);
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pool<RTLIL::Cell*> cell_list;
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wire2driver.find(sigmap(it.second), cell_list);
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queue.clear();
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for (auto c : cell_list) {
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for (auto bit : bits)
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for (auto c : wire2driver[bit])
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if (unused.count(c))
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if (unused.count(c))
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new_queue.insert(c);
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queue.insert(c), unused.erase(c);
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}
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}
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}
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}
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queue.swap(new_queue);
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}
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}
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unused.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
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for (auto cell : unused) {
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for (auto cell : unused) {
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if (verbose)
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if (verbose)
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log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
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log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
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