riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Removed forgotten debug code

This commit is contained in:
Andrew Zonenberg 2016-04-01 23:39:32 -07:00
parent 2386885f22
commit 87e7cd9fbd
1 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/greenpak4/greenpak4_counters.cc
View File

@ -347,8 +347,6 @@ void greenpak4_counters_worker(
log_id(extract.rwire->name), log_id(extract.rwire->name),
count_reg_src.c_str()); count_reg_src.c_str());
log("blah");
//Wipe all of the old connections to the ALU //Wipe all of the old connections to the ALU
cell->unsetPort("\\A"); cell->unsetPort("\\A");
cell->unsetPort("\\B"); cell->unsetPort("\\B");
@ -362,9 +360,7 @@ void greenpak4_counters_worker(
cell->unsetParam("\\B_SIGNED"); cell->unsetParam("\\B_SIGNED");
cell->unsetParam("\\B_WIDTH"); cell->unsetParam("\\B_WIDTH");
cell->unsetParam("\\Y_WIDTH"); cell->unsetParam("\\Y_WIDTH");
log("asdf");
//Change the cell type //Change the cell type
cell->type = celltype; cell->type = celltype;
@ -382,8 +378,6 @@ void greenpak4_counters_worker(
cell->setPort("\\RST", RTLIL::SigSpec(false)); cell->setPort("\\RST", RTLIL::SigSpec(false));
} }
log("world");
//Hook up other stuff //Hook up other stuff
cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value)); cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));