celledges: Add read ports arst paths

kernel/celledges.cc

@@ -316,8 +316,11 @@ void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 	int width = cell->getParam(ID::WIDTH).as_int();
 
 	for (int i = 0; i < n_rd_ports; i++) {
-		if (rd_clk_enable[i] != State::S0)
+		if (rd_clk_enable[i] != State::S0) {
+			for (int k = 0; k < width; k++)
+				db->add_edge(cell, ID::RD_ARST, i, ID::RD_DATA, i * width + k, -1);
 			continue;
+		}
 
 		for (int j = 0; j < abits; j++)
 			for (int k = 0; k < width; k++)
@@ -329,13 +332,17 @@ void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
 	log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
-
-	if (cell->getParam(ID::CLK_ENABLE).as_bool())
-		return;
-
 	int abits = cell->getParam(ID::ABITS).as_int();
 	int width = cell->getParam(ID::WIDTH).as_int();
 
+	if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
+		if (cell->type == ID($memrd_v2)) {
+			for (int k = 0; k < width; k++)
+				db->add_edge(cell, ID::ARST, 0, ID::DATA, k, -1);
+		}
+		return;
+	}
+
 	for (int j = 0; j < abits; j++)
 		for (int k = 0; k < width; k++)
 			db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);

tests/various/check_4.ys

@@ -0,0 +1,29 @@
+# loop involving the asynchronous reset on a memory port
+design -reset
+read -vlog2k <<EOF
+module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
+	reg [3:0] mem [15:0];
+	reg [5:0] i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] = i * 371;
+	end
+
+	wire arst = !data[0];
+
+	always @(posedge arst, posedge clk) begin
+		if (arst)		
+			data <= 4'hx;
+		else
+			data <= mem[addr];
+	end
+endmodule
+EOF
+hierarchy -top top
+proc
+opt -keepdc
+memory_dff
+opt_clean
+logger -nowarn "found logic loop in module pingpong:"
+logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
+check -assert