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Fixing compiler warning/issues. Moving test script to the correct place

This commit is contained in:
Diego H 2019-12-16 10:23:45 -06:00
parent f3f59910eb
commit 87e21b0122
2 changed files with 14 additions and 14 deletions
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16
passes/memory/memory_bram.cc
View File

@ -821,8 +821,8 @@ grow_read_ports:;
log(" Updated properties: dups=%d waste=%d efficiency=%d\n",
match_properties["dups"], match_properties["waste"], match_properties["efficiency"]);
for (auto& iter: match.attr_match) {
for (auto& iter: iter.second) {
for (auto iter: match.attr_match) {
for (auto iter: iter.second) {
auto it = cell->attributes.find(iter.first);
if (iter.second.empty()) {
@ -1124,8 +1124,8 @@ void handle_cell(Cell *cell, const rules_t &rules)
goto next_match_rule;
}
for (auto& iter: match.attr_match) {
for (auto& iter: iter.second) {
for (auto iter: match.attr_match) {
for (auto iter: iter.second) {
auto it = cell->attributes.find(iter.first);
if (it != cell->attributes.end()) {
@ -1149,10 +1149,10 @@ void handle_cell(Cell *cell, const rules_t &rules)
if (!it->second.empty()) {
if (it->second.decode_string().length() == 1)
it->second = it->second.as_string().back();
if (!it->second.decode_string().compare(iter.second.decode_string()))
goto next_match_rule;
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
if (!it->second.decode_string().compare(iter.second.decode_string()))
goto next_match_rule;
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
}
}
}

12
tests/arch/common/memory_attributes/attributes_test.ys → tests/arch/xilinx/attributes_test.ys
View File

@ -1,5 +1,5 @@
# Check that blockram memory without parameters is not modified
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top block_ram
synth_xilinx -top block_ram
cd block_ram # Constrain all select calls below inside the top module
@ -7,7 +7,7 @@ select -assert-count 1 t:RAMB18E1
# Check that distributed memory without parameters is not modified
design -reset
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top distributed_ram
synth_xilinx -top distributed_ram
cd distributed_ram # Constrain all select calls below inside the top module
@ -15,7 +15,7 @@ select -assert-count 8 t:RAM32X1D
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
prep
setattr -mod -set ram_style "distributed" block_ram
synth_xilinx -top block_ram
@ -24,7 +24,7 @@ select -assert-count 32 t:RAM128X1D
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
prep
setattr -mod -set logic_block 1 block_ram
synth_xilinx -top block_ram
@ -34,14 +34,14 @@ select -assert-count 32 t:RAM128X1D
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
synth_xilinx -top distributed_ram_manual
cd distributed_ram_manual # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
design -reset
read_verilog attributes_test.v
read_verilog ../common/memory_attributes/attributes_test.v
synth_xilinx -top distributed_ram_manual_syn
cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1