From 87e21b0122bd682db8aeffae3e1ac503c9cea2d2 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 16 Dec 2019 10:23:45 -0600 Subject: [PATCH] Fixing compiler warning/issues. Moving test script to the correct place --- passes/memory/memory_bram.cc | 16 ++++++++-------- .../attributes_test.ys | 12 ++++++------ 2 files changed, 14 insertions(+), 14 deletions(-) rename tests/arch/{common/memory_attributes => xilinx}/attributes_test.ys (81%) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 10b48e321..703e87f05 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -821,8 +821,8 @@ grow_read_ports:; log(" Updated properties: dups=%d waste=%d efficiency=%d\n", match_properties["dups"], match_properties["waste"], match_properties["efficiency"]); - for (auto& iter: match.attr_match) { - for (auto& iter: iter.second) { + for (auto iter: match.attr_match) { + for (auto iter: iter.second) { auto it = cell->attributes.find(iter.first); if (iter.second.empty()) { @@ -1124,8 +1124,8 @@ void handle_cell(Cell *cell, const rules_t &rules) goto next_match_rule; } - for (auto& iter: match.attr_match) { - for (auto& iter: iter.second) { + for (auto iter: match.attr_match) { + for (auto iter: iter.second) { auto it = cell->attributes.find(iter.first); if (it != cell->attributes.end()) { @@ -1149,10 +1149,10 @@ void handle_cell(Cell *cell, const rules_t &rules) if (!it->second.empty()) { if (it->second.decode_string().length() == 1) it->second = it->second.as_string().back(); - if (!it->second.decode_string().compare(iter.second.decode_string())) - goto next_match_rule; - log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", - log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); + if (!it->second.decode_string().compare(iter.second.decode_string())) + goto next_match_rule; + log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n", + log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str()); } } } diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys similarity index 81% rename from tests/arch/common/memory_attributes/attributes_test.ys rename to tests/arch/xilinx/attributes_test.ys index 4e06a35e7..4c881b280 100644 --- a/tests/arch/common/memory_attributes/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -1,5 +1,5 @@ # Check that blockram memory without parameters is not modified -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram synth_xilinx -top block_ram cd block_ram # Constrain all select calls below inside the top module @@ -7,7 +7,7 @@ select -assert-count 1 t:RAMB18E1 # Check that distributed memory without parameters is not modified design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram synth_xilinx -top distributed_ram cd distributed_ram # Constrain all select calls below inside the top module @@ -15,7 +15,7 @@ select -assert-count 8 t:RAM32X1D # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set ram_style "distributed" block_ram synth_xilinx -top block_ram @@ -24,7 +24,7 @@ select -assert-count 32 t:RAM128X1D # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set logic_block 1 block_ram synth_xilinx -top block_ram @@ -34,14 +34,14 @@ select -assert-count 32 t:RAM128X1D # Set ram_style block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual cd distributed_ram_manual # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual_syn cd distributed_ram_manual_syn # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1