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Merge pull request #4321 from YosysHQ/fix_read_verilog_defaults 

read_verilog: Add missing defaults for flags
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N. Engelhardt 2024-05-07 21:11:42 +02:00 committed by GitHub
parent 71f2540cd8 df95ea824b
commit 8735107c60
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1 changed files with 3 additions and 0 deletions
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frontends/verilog/verilog_frontend.cc
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@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yydebug = false; frontend_verilog_yydebug = false;
sv_mode = false; sv_mode = false;
formal_mode = false; formal_mode = false;
noassert_mode = false;
noassume_mode = false;
norestrict_mode = false; norestrict_mode = false;
assume_asserts_mode = false; assume_asserts_mode = false;
assert_assumes_mode = false;
lib_mode = false; lib_mode = false;
specify_mode = false; specify_mode = false;
default_nettype_wire = true; default_nettype_wire = true;