riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #386 from azonenberg/gpak-counters 

Bug fixes to GP_COUNTx and GP_PGEN cells in GreenPAK technology library
This commit is contained in:
Clifford Wolf 2017-08-16 15:58:29 +02:00 committed by GitHub
parent e9918365fd e6eaf487b6
commit 864498527a
1 changed files with 82 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

131
techlibs/greenpak4/cells_sim_digital.v
View File

@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
if(RST)
count <= 0;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
if(!RST)
count <= 0;
end
end
end
@ -145,19 +147,19 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
count <= COUNT_TO;
if(count == 14'h3fff && UP)
if(count == 0)
count <= COUNT_TO;
end
//Resets
if(RST) begin
@ -173,19 +175,19 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
count <= COUNT_TO;
if(count == 14'h3fff && UP)
if(count == 0)
count <= COUNT_TO;
end
//Resets
if(!RST) begin
@ -218,19 +220,19 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
else begin
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
count <= COUNT_TO;
if(count == 14'h3fff && UP)
if(count == 0)
count <= COUNT_TO;
end
end
@ -287,16 +289,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
count <= COUNT_TO;
if(count == 8'hff && UP)
if(count == 0)
count <= COUNT_TO;
end
//Resets
if(RST) begin
@ -315,16 +318,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
count <= COUNT_TO;
if(count == 8'hff && UP)
if(count == 0)
count <= COUNT_TO;
end
//Resets
if(!RST) begin
@ -357,20 +361,19 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
else begin
//Main counter
if(KEEP) begin
end
else if(UP)
else if(UP) begin
count <= count + 1'd1;
else
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
//Wrapping
if(count == 0 && !UP)
if(count == 0)
count <= COUNT_TO;
if(count == 8'hff && UP)
count <= COUNT_TO;
end
end
end
@ -421,23 +424,25 @@ module GP_COUNT8(
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
if(RST)
count <= 0;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
if(!RST)
count <= 0;
end
end
end
@ -737,19 +742,23 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg[3:0] count = 0;
always @(posedge CLK) begin
always @(posedge CLK, negedge nRST) begin
if(!nRST)
OUT <= PATTERN_DATA[0];
count <= 0;
else begin
count <= count + 1;
OUT <= PATTERN_DATA[count];
count <= count - 1'h1;
if(count == 0)
count <= COUNT_MAX;
end
end
if( (count + 1) == PATTERN_LEN)
count <= 0;
end
end
always @(*)
OUT = PATTERN_DATA[count];
endmodule