From 66b256d40e8762abd1c43e1c5d37d93fb57fc84e Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 14 Aug 2017 16:08:54 -0700
Subject: [PATCH 1/4] Fixed bug where GP_COUNTx_ADV would wrap even when KEEP
 was high

---
 techlibs/greenpak4/cells_sim_digital.v | 94 +++++++++++++-------------
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 3ed80005b..84a5dd049 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -145,19 +145,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
 
-					//Main counter
 					if(KEEP) begin
 					end
 					else if(UP)
 						count		<= count + 1'd1;
-					else
+						if(count == 14'h3fff)
+							count	<= COUNT_TO;
+					else begin
 						count		<= count - 1'd1;
 
-					//Wrapping
-					if(count == 0 && !UP)
-						count	<= COUNT_TO;
-					if(count == 14'h3fff && UP)
-						count	<= COUNT_TO;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 
 					//Resets
 					if(RST) begin
@@ -173,19 +172,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
 
-					//Main counter
 					if(KEEP) begin
 					end
 					else if(UP)
 						count		<= count + 1'd1;
-					else
+						if(count == 14'h3fff)
+							count	<= COUNT_TO;
+					else begin
 						count		<= count - 1'd1;
 
-					//Wrapping
-					if(count == 0 && !UP)
-						count	<= COUNT_TO;
-					if(count == 14'h3fff && UP)
-						count	<= COUNT_TO;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 
 					//Resets
 					if(!RST) begin
@@ -218,19 +216,18 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 					else begin
 
-						//Main counter
 						if(KEEP) begin
 						end
 						else if(UP)
 							count		<= count + 1'd1;
-						else
+							if(count == 14'h3fff)
+								count	<= COUNT_TO;
+						else begin
 							count		<= count - 1'd1;
 
-						//Wrapping
-						if(count == 0 && !UP)
-							count	<= COUNT_TO;
-						if(count == 14'h3fff && UP)
-							count	<= COUNT_TO;
+							if(count == 0)
+								count	<= COUNT_TO;
+						end
 
 					end
 
@@ -289,14 +286,14 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					end
 					else if(UP)
 						count		<= count + 1'd1;
-					else
+						if(count == 8'hff)
+							count	<= COUNT_TO;
+					else begin
 						count		<= count - 1'd1;
 
-					//Wrapping
-					if(count == 0 && !UP)
-						count	<= COUNT_TO;
-					if(count == 8'hff && UP)
-						count	<= COUNT_TO;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 
 					//Resets
 					if(RST) begin
@@ -317,14 +314,14 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					end
 					else if(UP)
 						count		<= count + 1'd1;
-					else
+						if(count == 8'hff)
+							count	<= COUNT_TO;
+					else begin
 						count		<= count - 1'd1;
 
-					//Wrapping
-					if(count == 0 && !UP)
-						count	<= COUNT_TO;
-					if(count == 8'hff && UP)
-						count	<= COUNT_TO;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 
 					//Resets
 					if(!RST) begin
@@ -357,19 +354,18 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 
 					else begin
 
-						//Main counter
 						if(KEEP) begin
 						end
 						else if(UP)
 							count		<= count + 1'd1;
-						else
+							if(count == 8'hff)
+								count	<= COUNT_TO;
+						else begin
 							count		<= count - 1'd1;
 
-						//Wrapping
-						if(count == 0 && !UP)
-							count	<= COUNT_TO;
-						if(count == 8'hff && UP)
-							count	<= COUNT_TO;
+							if(count == 0)
+								count	<= COUNT_TO;
+						end
 
 					end
 
@@ -737,20 +733,24 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	parameter PATTERN_DATA = 16'h0;
 	parameter PATTERN_LEN = 5'd16;
 
+	localparam COUNT_MAX =  PATTERN_LEN - 1'h1;
+
 	reg[3:0] count = 0;
 	always @(posedge CLK) begin
-		if(!nRST)
-			OUT <= PATTERN_DATA[0];
+		if(!nRST) begin
+			count	<= COUNT_MAX;
+		end
 
 		else begin
-			count <= count + 1;
-			OUT <= PATTERN_DATA[count];
-
-			if( (count + 1) == PATTERN_LEN)
-				count <= 0;
+			count	<= count - 1'h1;
+			if(count == 0)
+				count <= COUNT_MAX;
 		end
 	end
 
+	always @(*)
+		OUT	= PATTERN_DATA[count];
+
 endmodule
 
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);

From e5109847c9a6c4b34a2d78442758773adfea2f4f Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 14 Aug 2017 16:28:59 -0700
Subject: [PATCH 2/4] Fixed bug in GP_COUNTx model

---
 techlibs/greenpak4/cells_sim_digital.v | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 84a5dd049..5d9d67750 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -147,10 +147,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 14'h3fff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -174,10 +175,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 14'h3fff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -218,10 +220,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 						if(KEEP) begin
 						end
-						else if(UP)
+						else if(UP) begin
 							count		<= count + 1'd1;
 							if(count == 14'h3fff)
 								count	<= COUNT_TO;
+						end
 						else begin
 							count		<= count - 1'd1;
 
@@ -284,10 +287,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					//Main counter
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 8'hff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -312,10 +316,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					//Main counter
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 8'hff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -356,17 +361,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 
 						if(KEEP) begin
 						end
-						else if(UP)
+						else if(UP) begin
 							count		<= count + 1'd1;
 							if(count == 8'hff)
 								count	<= COUNT_TO;
+						end
 						else begin
 							count		<= count - 1'd1;
 
 							if(count == 0)
 								count	<= COUNT_TO;
 						end
-
 					end
 
 				end

From 3a404be62a7b7fcc435857e20aa6c528f373b81c Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 14 Aug 2017 17:15:56 -0700
Subject: [PATCH 3/4] Updated PGEN model to have level triggered reset (matches
 actual hardware behavior

---
 techlibs/greenpak4/cells_sim_digital.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 5d9d67750..6fba941a0 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	localparam COUNT_MAX =  PATTERN_LEN - 1'h1;
 
 	reg[3:0] count = 0;
-	always @(posedge CLK) begin
-		if(!nRST) begin
-			count	<= COUNT_MAX;
-		end
+	always @(posedge CLK, negedge nRST) begin
+
+		if(!nRST)
+			count	<= 0;
 
 		else begin
 			count	<= count - 1'h1;

From e6eaf487b6d46804641c67325082210e6f3d6d64 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 15 Aug 2017 00:50:31 -0700
Subject: [PATCH 4/4] Fixed more issues with GreenPAK counter sim models

---
 techlibs/greenpak4/cells_sim_digital.v | 42 ++++++++++++++------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 6fba941a0..043cd18d4 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(RST)
-						count	<= 0;
+						count		<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(!RST)
-						count	<= 0;
+						count		<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
@@ -88,7 +90,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 			"LEVEL": begin
 				always @(posedge CLK, posedge RST) begin
 					if(RST)
-						count	<= 0;
+						count		<= 0;
 
 					else begin
 						count		<= count - 1'd1;
@@ -422,23 +424,25 @@ module GP_COUNT8(
 
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(RST)
 						count	<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(!RST)
 						count	<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end