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Fixed cellaigs port extending

This commit is contained in:
Clifford Wolf 2015-06-10 07:16:30 +02:00
parent 66f9ee412a
commit 85287295b2
3 changed files with 11 additions and 3 deletions
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2
kernel/cellaigs.cc
View File

@ -77,7 +77,7 @@ struct AigMaker
if (portbit >= GetSize(cell->getPort(portname))) {
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
return bool_node(!inverter);
return bool_node(inverter);
}
AigNode node;

5
passes/techmap/aig.cc
View File

@ -90,12 +90,13 @@ struct AigPass : public Pass {
bit = cell->getPort(node.portname)[node.portbit];
} else if (node.left_parent < 0 && node.right_parent < 0) {
bit = node.inverter ? State::S0 : State::S1;
goto skip_inverter;
} else {
SigBit A = sigs.at(node.left_parent);
SigBit B = sigs.at(node.right_parent);
if (nand_mode && node.inverter) {
bit = module->NandGate(NEW_ID, A, B);
goto nand_inverter;
goto skip_inverter;
} else {
pair<int, int> key(node.left_parent, node.right_parent);
if (and_cache.count(key))
@ -108,7 +109,7 @@ struct AigPass : public Pass {
if (node.inverter)
bit = module->NotGate(NEW_ID, bit);
nand_inverter:
skip_inverter:
for (auto &op : node.outports)
module->connect(cell->getPort(op.first)[op.second], bit);

7
passes/tests/test_cell.cc
View File

@ -536,6 +536,9 @@ struct TestCellPass : public Pass {
log(" -simlib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n");
log(" -aig\n");
log(" instead of calling \"techmap\", call \"aig\"\n");
log("\n");
log(" -muxdiv\n");
log(" when creating test benches with dividers, create an additional mux\n");
log(" to mask out the division-by-zero case\n");
@ -600,6 +603,10 @@ struct TestCellPass : public Pass {
techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
continue;
}
if (args[argidx] == "-aig") {
techmap_cmd = "aig";
continue;
}
if (args[argidx] == "-muxdiv") {
muxdiv = true;
continue;