riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

add family and ability to disable carry chains

This commit is contained in:
Miodrag Milanovic 2024-03-01 11:11:23 +01:00
parent b3f59c9820
commit 8374f0336d
1 changed files with 34 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
techlibs/nanoxplore/synth_nanoxplore.cc
View File

@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com> * Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
@ -45,6 +46,15 @@ struct SynthNanoXplorePass : public ScriptPass
log(" -top <module>\n"); log(" -top <module>\n");
log(" use the specified module as top module\n"); log(" use the specified module as top module\n");
log("\n"); log("\n");
log(" -family <family>\n");
log(" run synthesis for the specified NanoXplore architecture\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" supported values:\n");
log(" - medium: NG-Medium\n");
log(" - large: NG-Large\n");
log(" - ultra: NG-Ultra\n");
log(" - u300: NG-Ultra300\n");
log("\n");
log(" -json <file>\n"); log(" -json <file>\n");
log(" write the design to the specified JSON file. writing of an output file\n"); log(" write the design to the specified JSON file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n"); log(" is omitted if this parameter is not specified.\n");
@ -60,21 +70,26 @@ struct SynthNanoXplorePass : public ScriptPass
log(" -abc9\n"); log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n"); log("\n");
log(" -nocy\n");
log(" do not map adders to CY cells\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, json_file; string top_opt, json_file, family;
bool flatten, abc9; bool flatten, abc9, nocy;
void clear_flags() override void clear_flags() override
{ {
top_opt = "-auto-top"; top_opt = "-auto-top";
json_file = ""; json_file = "";
family = "";
flatten = true; flatten = true;
abc9 = false; abc9 = false;
nocy = false;
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -89,6 +104,10 @@ struct SynthNanoXplorePass : public ScriptPass
top_opt = "-top " + args[++argidx]; top_opt = "-top " + args[++argidx];
continue; continue;
} }
if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
family = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) { if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx]; json_file = args[++argidx];
continue; continue;
@ -113,10 +132,19 @@ struct SynthNanoXplorePass : public ScriptPass
abc9 = true; abc9 = true;
continue; continue;
} }
if (args[argidx] == "-nocy") {
nocy = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (family.empty()) {
log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
family = "ultra";
}
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
@ -175,13 +203,15 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("map_gates")) if (check_label("map_gates"))
{ {
run("techmap"); if (nocy)
run("techmap");
else
run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
run("opt -fast"); run("opt -fast");
} }
if (check_label("map_ffs")) if (check_label("map_ffs"))
{ {
run("techmap");
run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0"); run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
run("techmap -map +/nanoxplore/cells_map.v"); run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef"); run("opt_expr -undriven -mux_undef");