mirror of https://github.com/YosysHQ/yosys.git
Fixed shift ops with large right hand side
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@ -241,7 +241,7 @@ struct SatGen
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{
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{
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std::vector<int> tmp_shifted(tmp.size());
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std::vector<int> tmp_shifted(tmp.size());
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for (size_t j = 0; j < tmp.size(); j++) {
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for (size_t j = 0; j < tmp.size(); j++) {
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int idx = j + (1 << i) * (shift_left ? -1 : +1);
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int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left ? -1 : +1);
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tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE;
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tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE;
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}
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}
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tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);
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tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);
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@ -446,7 +446,7 @@ generate
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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\$shift #(
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.WIDTH(WIDTH),
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.WIDTH(WIDTH),
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.SHIFT(0 - (2 ** i))
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.SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
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) sh (
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) sh (
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.X(0),
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.X(0),
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.A(unshifted),
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.A(unshifted),
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@ -499,7 +499,7 @@ generate
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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\$shift #(
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.WIDTH(WIDTH),
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.WIDTH(WIDTH),
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.SHIFT(2 ** i)
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.SHIFT(2 ** (i > 30 ? 30 : i))
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) sh (
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) sh (
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.X(0),
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.X(0),
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.A(unshifted),
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.A(unshifted),
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@ -552,7 +552,7 @@ generate
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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\$shift #(
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.WIDTH(WIDTH),
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.WIDTH(WIDTH),
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.SHIFT(0 - (2 ** i))
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.SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
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) sh (
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) sh (
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.X(0),
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.X(0),
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.A(unshifted),
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.A(unshifted),
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@ -614,7 +614,7 @@ generate
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
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\$shift #(
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\$shift #(
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.WIDTH(WIDTH),
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.WIDTH(WIDTH),
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.SHIFT(2 ** i)
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.SHIFT(2 ** (i > 30 ? 30 : i))
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) sh (
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) sh (
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.X(A_SIGNED && A[A_WIDTH-1]),
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.X(A_SIGNED && A[A_WIDTH-1]),
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.A(unshifted),
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.A(unshifted),
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@ -800,7 +800,7 @@ input [B_WIDTH-1:0] B;
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output Y;
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output Y;
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wire carry, carry_sign;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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@ -825,7 +825,7 @@ input [B_WIDTH-1:0] B;
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output Y;
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output Y;
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wire carry, carry_sign;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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@ -8,3 +8,43 @@ module test01(a, y);
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assign y = ~a >> 4;
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assign y = ~a >> 4;
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endmodule
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endmodule
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module test02(a, y);
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input signed [3:0] a;
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output signed [4:0] y;
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assign y = (~a) >> 1;
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endmodule
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module test03(a, b, y);
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input [2:0] a;
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input signed [1:0] b;
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output y;
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assign y = ~(a >>> 1) == b;
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endmodule
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module test04(a, y);
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input a;
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output [1:0] y;
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assign y = ~(a - 1'b0);
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endmodule
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module test05(a, y);
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input a;
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output y;
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assign y = 12345 >> {a, 32'd0};
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endmodule
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module test06(a, b, c, y);
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input signed [3:0] a;
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input signed [1:0] b;
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input signed [1:0] c;
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output [5:0] y;
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assign y = (a >> b) >>> c;
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endmodule
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module test07(a, b, y);
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input signed [1:0] a;
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input signed [2:0] b;
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output y;
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assign y = 2'b11 != a+b;
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endmodule
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