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Added verilog frontend -ignore_redef option

This commit is contained in:
Clifford Wolf 2013-11-24 19:57:42 +01:00
parent 20175afd29
commit 7d9a90396d
3 changed files with 19 additions and 5 deletions
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11
frontends/ast/ast.cc
View File

@ -763,7 +763,7 @@ static AstModule* process_module(AstNode *ast)
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt)
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef)
{
current_ast = ast;
flag_dump_ast1 = dump_ast1;
@ -777,9 +777,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
if (design->modules.count((*it)->str) != 0)
log_error("Re-definition of module `%s' at %s:%d!\n",
if (design->modules.count((*it)->str) != 0) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log_error("Ignoring re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
design->modules[(*it)->str] = process_module(*it);
}
}

2
frontends/ast/ast.h
View File

@ -219,7 +219,7 @@ namespace AST
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false);
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false);
// parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions

11
frontends/verilog/verilog_frontend.cc
View File

@ -96,6 +96,10 @@ struct VerilogFrontend : public Frontend {
log(" don't perform basic optimizations (such as const folding) in the\n");
log(" high-level front-end.\n");
log("\n");
log(" -ignore_redef\n");
log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message.)\n");
log("\n");
log(" -Dname[=definition]\n");
log(" define the preprocessor symbol 'name' and set its optional value\n");
log(" 'definition'\n");
@ -117,6 +121,7 @@ struct VerilogFrontend : public Frontend {
bool flag_nopp = false;
bool flag_lib = false;
bool flag_noopt = false;
bool flag_ignore_redef = false;
std::map<std::string, std::string> defines_map;
std::list<std::string> include_dirs;
frontend_verilog_yydebug = false;
@ -170,6 +175,10 @@ struct VerilogFrontend : public Frontend {
flag_noopt = true;
continue;
}
if (arg == "-ignore_redef") {
flag_ignore_redef = true;
continue;
}
if (arg.compare(0,2,"-D") == 0) {
size_t equal = arg.find('=',2); // returns string::npos it not found
std::string name = arg.substr(2,equal-2);
@ -211,7 +220,7 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yyparse();
frontend_verilog_yylex_destroy();
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_ignore_redef);
if (!flag_nopp)
fclose(fp);