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Add comment with expected behavior for latches,tribuf tests;Update adffs test

This commit is contained in:
SergeyDegtyar 2019-09-11 17:01:19 +03:00 committed by Miodrag Milanovic
parent 489444bcba
commit 7bc8f0c2e2
4 changed files with 11 additions and 14 deletions
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18
tests/xilinx/adffs.v
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@ -22,30 +22,26 @@ module adffn
q <= d; q <= d;
endmodule endmodule
module dffsr module dffs
( input d, clk, pre, clr, output reg q ); ( input d, clk, pre, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk )
if ( clr ) if ( pre )
q <= 1'b0;
else if ( pre )
q <= 1'b1; q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr module ndffnr
( input d, clk, pre, clr, output reg q ); ( input d, clk, pre, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( negedge clk, negedge pre, negedge clr ) always @( negedge clk )
if ( !clr ) if ( !clr )
q <= 1'b0; q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
@ -58,7 +54,7 @@ input a,
output b,b1,b2,b3 output b,b1,b2,b3
); );
dffsr u_dffsr ( dffs u_dffs (
.clk (clk ), .clk (clk ),
.clr (clr), .clr (clr),
.pre (pre), .pre (pre),
@ -66,7 +62,7 @@ dffsr u_dffsr (
.q (b ) .q (b )
); );
ndffnsnr u_ndffnsnr ( ndffnr u_ndffnr (
.clk (clk ), .clk (clk ),
.clr (clr), .clr (clr),
.pre (pre), .pre (pre),

5
tests/xilinx/adffs.ys
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@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 3 t:FDRE select -assert-count 3 t:FDRE
select -assert-count 1 t:FDRE_1 select -assert-count 1 t:FDRE_1
select -assert-count 4 t:LUT2 select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3 select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D
select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D

1
tests/xilinx/latches.ys
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@ -15,5 +15,6 @@ flatten
cd top cd top
select -assert-count 1 t:LUT1 select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT3 select -assert-count 2 t:LUT3
#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
select -assert-count 3 t:$_DLATCH_P_ select -assert-count 3 t:$_DLATCH_P_
select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D

1
tests/xilinx/tribuf.ys
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@ -7,5 +7,6 @@ synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
select -assert-count 1 t:$_TBUF_ select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D select -assert-none t:$_TBUF_ %% t:* %D