mirror of https://github.com/YosysHQ/yosys.git
Add log_assert to ensure no loops
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@ -334,7 +334,21 @@ struct XAigerWriter
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pool<RTLIL::Module*> abc_carry_modules;
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pool<RTLIL::Module*> abc_carry_modules;
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toposort.sort();
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d", i++);
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for (auto cell : it)
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log(" %s", log_id(cell));
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log("\n");
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}
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#endif
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log_assert(no_loops);
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for (auto cell_name : toposort.sorted) {
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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RTLIL::Cell *cell = module->cell(cell_name);
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RTLIL::Module* box_module = module->design->module(cell->type);
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RTLIL::Module* box_module = module->design->module(cell->type);
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