mirror of https://github.com/YosysHQ/yosys.git
parent
7129a03083
commit
78560aac86
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@ -430,7 +430,6 @@ struct WreduceWorker
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for (auto w : module->wires())
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for (auto w : module->wires())
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complete_wires.insert(mi.sigmap(w));
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complete_wires.insert(mi.sigmap(w));
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std::vector<std::pair<Wire*,Wire*>> swap_wire_names;
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for (auto w : module->selected_wires())
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for (auto w : module->selected_wires())
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{
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{
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int unused_top_bits = 0;
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int unused_top_bits = 0;
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@ -455,12 +454,9 @@ struct WreduceWorker
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log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
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log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
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Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
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Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
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swap_wire_names.emplace_back(w, nw);
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module->swap_names(w, nw);
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}
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}
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for (const auto &i : swap_wire_names)
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module->swap_names(i.first, i.second);
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if (!remove_init_bits.empty()) {
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if (!remove_init_bits.empty()) {
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for (auto w : module->wires()) {
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for (auto w : module->wires()) {
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if (w->attributes.count("\\init")) {
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if (w->attributes.count("\\init")) {
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