riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix first divergence in #1178

This commit is contained in:
Eddie Hung 2019-07-09 15:49:16 -07:00
parent 27b27b8781
commit 1122a2e067
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/opt/wreduce.cc
View File

@ -430,6 +430,7 @@ struct WreduceWorker
for (auto w : module->wires())
complete_wires.insert(mi.sigmap(w));
std::vector<std::pair<Wire*,Wire*>> swap_wire_names;
for (auto w : module->selected_wires())
{
int unused_top_bits = 0;
@ -454,9 +455,12 @@ struct WreduceWorker
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
swap_wire_names.emplace_back(w, nw);
}
for (const auto &i : swap_wire_names)
module->swap_names(i.first, i.second);
if (!remove_init_bits.empty()) {
for (auto w : module->wires()) {
if (w->attributes.count("\\init")) {