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Merge pull request #3971 from povik/equiv_simple-fixes 

Fixes to `equiv_simple`
This commit is contained in:
N. Engelhardt 2023-12-18 16:31:02 +01:00 committed by GitHub
parent 2615209dc1 1f1f43edd9
commit 78541be4d8
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 4 deletions
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8
passes/equiv/equiv_simple.cc
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@ -60,7 +60,7 @@ struct EquivSimpleWorker
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first)) if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : sigmap(conn.second)) { for (auto bit : sigmap(conn.second)) {
if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) { if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (!conn.first.in(ID::CLK, ID::C)) if (!conn.first.in(ID::CLK, ID::C))
next_seed.insert(bit); next_seed.insert(bit);
} else } else
@ -133,11 +133,9 @@ struct EquivSimpleWorker
for (auto bit_a : seed_a) for (auto bit_a : seed_a)
find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a); find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
next_seed_a.clear();
for (auto bit_b : seed_b) for (auto bit_b : seed_b)
find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b); find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
next_seed_b.clear();
pool<Cell*> short_cells_cone_a, short_cells_cone_b; pool<Cell*> short_cells_cone_a, short_cells_cone_b;
pool<SigBit> short_bits_cone_a, short_bits_cone_b; pool<SigBit> short_bits_cone_a, short_bits_cone_b;
@ -145,10 +143,12 @@ struct EquivSimpleWorker
if (short_cones) if (short_cones)
{ {
next_seed_a.clear();
for (auto bit_a : seed_a) for (auto bit_a : seed_a)
find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a); find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
next_seed_a.swap(seed_a); next_seed_a.swap(seed_a);
next_seed_b.clear();
for (auto bit_b : seed_b) for (auto bit_b : seed_b)
find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b); find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
next_seed_b.swap(seed_b); next_seed_b.swap(seed_b);
@ -364,7 +364,7 @@ struct EquivSimplePass : public Pass {
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module)); unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) if (!ct.cell_known(cell->type))
continue; continue;
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first)) if (yosys_celltypes.cell_output(cell->type, conn.first))