riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cellhelp: Rename short_desc to title

This commit is contained in:
Krystine Sherwin 2024-04-11 11:15:24 +12:00
parent 1e5a50ff3a
commit 784292626e
No known key found for this signature in database
3 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
kernel/register.cc
View File

@ -755,7 +755,7 @@ struct SimHelper {
else
return name;
}
string short_desc;
string title;
string ports;
string desc;
string code;
@ -887,8 +887,8 @@ struct HelpPass : public Pass {
// make header
string title_line;
if (cell.short_desc.length())
title_line = stringf("%s - %s", cell.name.c_str(), cell.short_desc.c_str());
if (cell.title.length())
title_line = stringf("%s - %s", cell.name.c_str(), cell.title.c_str());
else title_line = cell.name;
string underline = "\n";
underline.insert(0, title_line.length(), '=');
@ -988,7 +988,7 @@ struct HelpPass : public Pass {
SimHelper help_cell = cell_help_messages.cell_help.at(args[1]);
if (help_cell.ver == "2") {
log("\n %s %s\n", help_cell.name.c_str(), help_cell.ports.c_str());
log("\n%s\n", help_cell.short_desc.c_str());
log("\n%s\n", help_cell.title.c_str());
log("%s\n", help_cell.desc.c_str());
log("Run 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
log("\n");

4
techlibs/common/cellhelp.py
View File

@ -6,7 +6,7 @@ import json
class SimHelper:
name: str = ""
short_desc: str = ""
title: str = ""
ports: str = ""
desc: list[str]
code: list[str]
@ -18,7 +18,7 @@ class SimHelper:
def __str__(self) -> str:
val = "tempCell = {\n"
val += f' {json.dumps(self.name)},\n'
val += f' {json.dumps(self.short_desc)},\n'
val += f' {json.dumps(self.title)},\n'
val += f' {json.dumps(self.ports)},\n'
val += ' ' + json.dumps("\n".join(self.desc)) + ',\n'
val += ' ' + json.dumps("\n".join(self.code)) + ',\n'

2
techlibs/common/simlib.v
View File

@ -622,7 +622,7 @@ endmodule
// --------------------------------------------------------
//* ver 2
//* short_desc Arithmetic logic unit
//* title Arithmetic logic unit
//- A building block supporting both binary addition/subtraction operations, and
//- indirectly, comparison operations.
//- Typically created by the `alumacc` pass, which transforms: