From 784292626e9235ba52cc4946dd81e54a58ef5cec Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 11 Apr 2024 11:15:24 +1200
Subject: [PATCH] cellhelp: Rename short_desc to title

---
 kernel/register.cc          | 8 ++++----
 techlibs/common/cellhelp.py | 4 ++--
 techlibs/common/simlib.v    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/kernel/register.cc b/kernel/register.cc
index edf6ea7ba..fe3495dad 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -755,7 +755,7 @@ struct SimHelper {
 		else
 			return name;
 	}
-	string short_desc;
+	string title;
 	string ports;
 	string desc;
 	string code;
@@ -887,8 +887,8 @@ struct HelpPass : public Pass {
 
 		// make header
 		string title_line;
-		if (cell.short_desc.length())
-			title_line = stringf("%s - %s", cell.name.c_str(), cell.short_desc.c_str());
+		if (cell.title.length())
+			title_line = stringf("%s - %s", cell.name.c_str(), cell.title.c_str());
 		else title_line = cell.name;
 		string underline = "\n";
 		underline.insert(0, title_line.length(), '=');
@@ -988,7 +988,7 @@ struct HelpPass : public Pass {
 				SimHelper help_cell = cell_help_messages.cell_help.at(args[1]);
 				if (help_cell.ver == "2") {
 					log("\n    %s %s\n", help_cell.name.c_str(), help_cell.ports.c_str());
-					log("\n%s\n", help_cell.short_desc.c_str());
+					log("\n%s\n", help_cell.title.c_str());
 					log("%s\n", help_cell.desc.c_str());
 					log("Run 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
 					log("\n");
diff --git a/techlibs/common/cellhelp.py b/techlibs/common/cellhelp.py
index 4d40b73c0..312446ad4 100644
--- a/techlibs/common/cellhelp.py
+++ b/techlibs/common/cellhelp.py
@@ -6,7 +6,7 @@ import json
 
 class SimHelper:
     name: str = ""
-    short_desc: str = ""
+    title: str = ""
     ports: str = ""
     desc: list[str]
     code: list[str]
@@ -18,7 +18,7 @@ class SimHelper:
     def __str__(self) -> str:
         val = "tempCell = {\n"
         val += f'  {json.dumps(self.name)},\n'
-        val += f'  {json.dumps(self.short_desc)},\n'
+        val += f'  {json.dumps(self.title)},\n'
         val += f'  {json.dumps(self.ports)},\n'
         val += '  ' + json.dumps("\n".join(self.desc)) + ',\n'
         val += '  ' + json.dumps("\n".join(self.code)) + ',\n'
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 71bb58c41..96f143c2a 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -622,7 +622,7 @@ endmodule
 // --------------------------------------------------------
 
 //* ver 2
-//* short_desc Arithmetic logic unit
+//* title Arithmetic logic unit
 //- A building block supporting both binary addition/subtraction operations, and
 //- indirectly, comparison operations.
 //- Typically created by the `alumacc` pass, which transforms: