mirror of https://github.com/YosysHQ/yosys.git
Allow "hierarchy -generate" for $__ cells
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@ -41,7 +41,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
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for (auto i2 : i1.second->cells_)
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{
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RTLIL::Cell *cell = i2.second;
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if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0)
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if (design->has(cell->type))
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continue;
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if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
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continue;
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for (auto &pattern : celltypes)
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if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))
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