mirror of https://github.com/YosysHQ/yosys.git
Parse 'm' in xaiger
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b3341b4abb
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@ -27,6 +27,7 @@
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#include "aigerparse.h"
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#include "aigerparse.h"
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#include <boost/endian/buffers.hpp>
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#include <boost/endian/buffers.hpp>
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#include <boost/lexical_cast.hpp>
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YOSYS_NAMESPACE_BEGIN
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YOSYS_NAMESPACE_BEGIN
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@ -114,6 +115,14 @@ void AigerReader::parse_aiger()
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design->add(module);
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design->add(module);
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}
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}
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static uint32_t parse_xaiger_literal(std::istream &f)
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{
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boost::endian::big_uint32_buf_t l;
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if (f.readsome(reinterpret_cast<char*>(&l), sizeof(l)) != sizeof(l))
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log_error("Offset %ld: unable to read literal!\n", boost::lexical_cast<int64_t>(f.tellg()));
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return l.value();
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}
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void AigerReader::parse_xaiger()
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void AigerReader::parse_xaiger()
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{
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{
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std::string header;
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std::string header;
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@ -147,8 +156,52 @@ void AigerReader::parse_xaiger()
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// Parse footer (symbol table, comments, etc.)
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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unsigned l1;
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std::string s;
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std::string s;
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bool comment_seen = false;
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for (int c = f.peek(); c != EOF; c = f.peek()) {
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for (int c = f.peek(); c != EOF; c = f.peek()) {
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if (c == 'i' || c == 'l' || c == 'o') {
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if (comment_seen || c == 'c') {
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if (!comment_seen) {
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f.ignore(1);
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c = f.peek();
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if (c == '\n')
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break;
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f.ignore(1);
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comment_seen = true;
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}
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// XAIGER extensions
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if (c == 'm') {
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uint32_t dataSize = parse_xaiger_literal(f);
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uint32_t lutNum = parse_xaiger_literal(f);
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uint32_t lutSize = parse_xaiger_literal(f);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
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for (unsigned i = 0; i < lutNum; ++i) {
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(stringf("\\n%d", rootNodeID));
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log_assert(output_sig);
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug("\t%u\n", nodeID);
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RTLIL::Wire *wire = module->wire(stringf("\\n%d", nodeID));
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log_assert(wire);
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input_sig.append(wire);
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
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cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->setPort("\\A", input_sig);
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cell->setPort("\\Y", output_sig);
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}
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}
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else if (c == 'n') {
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// TODO: What is this?
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uint32_t n = parse_xaiger_literal(f);
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f.seekg(n);
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}
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}
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else if (c == 'i' || c == 'l' || c == 'o') {
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f.ignore(1);
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f.ignore(1);
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if (!(f >> l1 >> s))
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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@ -163,28 +216,11 @@ void AigerReader::parse_xaiger()
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else log_abort();
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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std::getline(f, line); // Ignore up to start of next line
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else if (c == 'c') {
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++line_count;
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f.ignore(1);
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if (f.peek() == '\n')
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break;
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if (f.peek() == 'm') {
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f.ignore(1);
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boost::endian::big_uint32_buf_t dataSize, lutNum, lutSize;
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if (f.readsome(reinterpret_cast<char*>(&dataSize), sizeof(dataSize)) != sizeof(dataSize))
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log_error("Line %u: unable to read dataSize!\n", line_count);
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if (f.readsome(reinterpret_cast<char*>(&lutNum), sizeof(lutNum)) != sizeof(lutNum))
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log_error("Line %u: unable to read lutNum!\n", line_count);
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if (f.readsome(reinterpret_cast<char*>(&lutSize), sizeof(lutSize)) != sizeof(lutSize))
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log_error("Line %u: unable to read lutSize!\n", line_count);
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log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize.value(), lutNum.value(), lutSize.value());
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break;
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}
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}
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}
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else
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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++line_count;
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}
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}
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module->fixup_ports();
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module->fixup_ports();
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@ -341,6 +377,7 @@ void AigerReader::parse_aiger_binary(bool create_and)
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// Parse inputs
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// Parse inputs
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for (unsigned i = 1; i <= I; ++i) {
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for (unsigned i = 1; i <= I; ++i) {
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log_debug("%d is an input\n", i);
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RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
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RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
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wire->port_input = true;
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wire->port_input = true;
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inputs.push_back(wire);
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inputs.push_back(wire);
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