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cutpoint: Improve efficiency by iterating over module ports instead of module wires.

This commit is contained in:
Alberto Gonzalez 2020-06-18 17:42:36 +00:00
parent dfde1cf1c5
commit 76dfa81790
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1 changed files with 10 additions and 9 deletions
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19
passes/sat/cutpoint.cc
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@ -126,15 +126,16 @@ struct CutpointPass : public Pass {
} }
vector<Wire*> rewrite_wires; vector<Wire*> rewrite_wires;
for (auto wire : module->wires()) { for (auto id : module->ports) {
if (!wire->port_input) RTLIL::Wire *wire = module->wire(id);
continue; if (wire->port_input) {
int bit_count = 0; int bit_count = 0;
for (auto &bit : sigmap(wire)) for (auto &bit : sigmap(wire))
if (cutpoint_bits.count(bit)) if (cutpoint_bits.count(bit))
bit_count++; bit_count++;
if (bit_count) if (bit_count)
rewrite_wires.push_back(wire); rewrite_wires.push_back(wire);
}
} }
for (auto wire : rewrite_wires) { for (auto wire : rewrite_wires) {