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Add synth_xilinx -nomux option

This commit is contained in:
Eddie Hung 2019-04-22 12:36:15 -07:00
parent 79fb291dbe
commit 75b96b1aff
2 changed files with 18 additions and 4 deletions
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2
techlibs/xilinx/cells_map.v
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@ -142,6 +142,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
endgenerate endgenerate
endmodule endmodule
`ifndef NO_MUXFN
module \$shiftx (A, B, Y); module \$shiftx (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
@ -219,3 +220,4 @@ module \$shiftx (A, B, Y);
end end
endgenerate endgenerate
endmodule endmodule
`endif // NO_MUXFN

20
techlibs/xilinx/synth_xilinx.cc
View File

@ -72,6 +72,9 @@ struct SynthXilinxPass : public Pass
log(" -nosrl\n"); log(" -nosrl\n");
log(" disable inference of shift registers\n"); log(" disable inference of shift registers\n");
log("\n"); log("\n");
log(" -nomux\n");
log(" disable inference of wide multiplexers\n");
log("\n");
log(" -run <from_label>:<to_label>\n"); log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n"); log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n"); log(" from label is synonymous to 'begin', and empty to label is\n");
@ -119,7 +122,7 @@ struct SynthXilinxPass : public Pass
log(" opt -fast\n"); log(" opt -fast\n");
log("\n"); log("\n");
log(" map_cells:\n"); log(" map_cells:\n");
log(" pmux2shiftx\n"); log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n");
log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass
bool nobram = false; bool nobram = false;
bool nodram = false; bool nodram = false;
bool nosrl = false; bool nosrl = false;
bool nomux = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -209,6 +213,10 @@ struct SynthXilinxPass : public Pass
nosrl = true; nosrl = true;
continue; continue;
} }
if (args[argidx] == "-nomux") {
nomux = true;
continue;
}
if (args[argidx] == "-abc9") { if (args[argidx] == "-abc9") {
abc = "abc9"; abc = "abc9";
continue; continue;
@ -291,8 +299,9 @@ struct SynthXilinxPass : public Pass
// shregmap -tech xilinx can cope with $shiftx and $mux // shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers, // cells for identifying variable-length shift registers,
// so attempt to convert $pmux-es to the former // so attempt to convert $pmux-es to the former
// Also: wide multiplexers inference benefits from this too // Also: wide multiplexer inference benefits from this too
Pass::call(design, "pmux2shiftx"); if (!nosrl || !nomux)
Pass::call(design, "pmux2shiftx");
if (!nosrl) { if (!nosrl) {
// shregmap operates on bit-level flops, not word-level, // shregmap operates on bit-level flops, not word-level,
@ -305,7 +314,10 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "shregmap -tech xilinx -minlen 3"); Pass::call(design, "shregmap -tech xilinx -minlen 3");
} }
Pass::call(design, "techmap -map +/xilinx/cells_map.v"); std::string define;
if (nomux)
define += " -D NO_MUXFN";
Pass::call(design, "techmap" + define + " -map +/xilinx/cells_map.v");
Pass::call(design, "clean"); Pass::call(design, "clean");
} }