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Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.

This commit is contained in:
Diego H 2019-12-12 17:32:58 -06:00
parent e33f407655
commit 751a18d7e9
2 changed files with 7 additions and 7 deletions
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10
techlibs/xilinx/xc7_xcu_brams.txt
View File

@ -1,4 +1,3 @@
bram $__XILINX_RAMB36_SDP bram $__XILINX_RAMB36_SDP
init 1 init 1
abits 9 abits 9
@ -72,6 +71,11 @@ bram $__XILINX_RAMB18_TDP
clkpol 2 3 clkpol 2 3
endbram endbram
# The "min bits" value were taken from:
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
# v1.14 ed., p 29-30, July, 2019.
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
match $__XILINX_RAMB36_SDP match $__XILINX_RAMB36_SDP
min bits 1024 min bits 1024
min efficiency 5 min efficiency 5
@ -102,7 +106,3 @@ match $__XILINX_RAMB18_TDP
shuffle_enable B shuffle_enable B
make_transp make_transp
endmatch endmatch
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
# v1.14 ed., p 29-30, July, 2019.

4
tests/arch/xilinx/memory_params.ys
View File

@ -37,10 +37,10 @@ cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1 select -assert-count 0 t:RAMB18E1
select -assert-count 4 t:RAM128X1D select -assert-count 4 t:RAM128X1D
# More than 18K bits and addr <= 36: -> RAMB36E1 # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
design -reset design -reset
read_verilog ../common/memory_params.v read_verilog ../common/memory_params.v
chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB36E1 select -assert-count 1 t:RAMB36E1