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quicklogic: fix double width read

This commit is contained in:
Krystine Sherwin 2023-11-30 09:16:12 +13:00 committed by Martin Povišer
parent 8d3b238b9b
commit 7513bfcbfe
2 changed files with 25 additions and 18 deletions
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41
tests/arch/common/blockram.v
View File

@ -71,27 +71,34 @@ endmodule // sync_ram_sdp_wwr
module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9 module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9
(input wire clk, write_enable, (
input wire [DATA_WIDTH-1:0] data_in, input wire clk_w, clk_r, write_enable,
input wire [ADDRESS_WIDTH-1:0] address_in_w, input wire [DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-2:0] address_in_r, input wire [ADDRESS_WIDTH-1:0] address_in_w,
output wire [(DATA_WIDTH*1)-1:0] data_out); input wire [ADDRESS_WIDTH_R-1:0] address_in_r,
output wire [WORD-1:0] data_out
);
localparam ADDRESS_WIDTH_R = ADDRESS_WIDTH-1;
localparam HWORD = DATA_WIDTH;
localparam WORD = 2*DATA_WIDTH;
localparam DEPTH = 2**ADDRESS_WIDTH_R;
localparam WORD = (DATA_WIDTH-1); reg [WORD-1:0] data_out_r;
localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD-1:0] memory [0:DEPTH-1];
reg [WORD:0] data_out_r0; always @(posedge clk_w) begin
reg [WORD:0] data_out_r1; if (write_enable)
reg [WORD:0] memory [0:DEPTH]; if (address_in_w[0]) // upper HWORD
memory[address_in_w>>1][WORD-1:HWORD] <= data_in;
else // lower HWORD
memory[address_in_w>>1][HWORD-1:0] <= data_in;
end
always @(posedge clk) begin always @(posedge clk_r) begin
if (write_enable) data_out_r <= memory[address_in_r];
memory[address_in_w] <= data_in; end
data_out_r0 <= memory[address_in_r<<1+0];
data_out_r1 <= memory[address_in_r<<1+1];
end
assign data_out = {data_out_r0, data_out_r1}; assign data_out = data_out_r;
endmodule // sync_ram_sdp_wrr endmodule // sync_ram_sdp_wrr

2
tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
View File

@ -36,7 +36,7 @@ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
# 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K)
([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
# two disjoint 18K memories can share a single TDP36K # two disjoint 18K memories can share a single TDP36K
([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),