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Use C++11 final/override keywords.

This commit is contained in:
whitequark 2020-06-18 23:34:52 +00:00
parent dfde1cf1c5
commit 7191dd16f9
220 changed files with 540 additions and 548 deletions
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4
backends/aiger/aiger.cc
View File

@ -681,7 +681,7 @@ struct AigerWriter
struct AigerBackend : public Backend {
AigerBackend() : Backend("aiger", "write design to AIGER file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -719,7 +719,7 @@ struct AigerBackend : public Backend {
log(" AIGER file happy.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool ascii_mode = false;
bool zinit_mode = false;

4
backends/aiger/xaiger.cc
View File

@ -731,7 +731,7 @@ struct XAigerWriter
struct XAigerBackend : public Backend {
XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -753,7 +753,7 @@ struct XAigerBackend : public Backend {
log(" write $_DFF_[NP]_ cells\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool ascii_mode = false, dff_mode = false;
std::string map_filename;

4
backends/blif/blif.cc
View File

@ -482,7 +482,7 @@ struct BlifDumper
struct BlifBackend : public Backend {
BlifBackend() : Backend("blif", "write design to BLIF file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -552,7 +552,7 @@ struct BlifBackend : public Backend {
log(" do not write definitions for the $true, $false and $undef wires.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::string top_module_name;
std::string buf_type, buf_in, buf_out;

4
backends/btor/btor.cc
View File

@ -1335,7 +1335,7 @@ struct BtorWorker
struct BtorBackend : public Backend {
BtorBackend() : Backend("btor", "write design to BTOR file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1359,7 +1359,7 @@ struct BtorBackend : public Backend {
log(" Output symbols for internal netnames (starting with '$')\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
string info_filename;

4
backends/cxxrtl/cxxrtl_backend.cc
View File

@ -2313,7 +2313,7 @@ struct CxxrtlBackend : public Backend {
static const int DEFAULT_DEBUG_LEVEL = 1;
CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -2535,7 +2535,7 @@ struct CxxrtlBackend : public Backend {
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool noflatten = false;
bool noproc = false;

4
backends/edif/edif.cc
View File

@ -90,7 +90,7 @@ struct EdifNames
struct EdifBackend : public Backend {
EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -126,7 +126,7 @@ struct EdifBackend : public Backend {
log("is targeted.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EDIF backend.\n");
std::string top_module_name;

4
backends/firrtl/firrtl.cc
View File

@ -1123,7 +1123,7 @@ struct FirrtlWorker
struct FirrtlBackend : public Backend {
FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1134,7 +1134,7 @@ struct FirrtlBackend : public Backend {
log(" pmuxtree\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = args.size(); // We aren't expecting any arguments.

8
backends/ilang/ilang_backend.cc
View File

@ -400,7 +400,7 @@ PRIVATE_NAMESPACE_BEGIN
struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang", "write design to ilang file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -413,7 +413,7 @@ struct IlangBackend : public Backend {
log(" only write selected parts of the design.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool selected = false;
@ -440,7 +440,7 @@ struct IlangBackend : public Backend {
struct DumpPass : public Pass {
DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -463,7 +463,7 @@ struct DumpPass : public Pass {
log(" like -outfile but append instead of overwrite\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool flag_m = false, flag_n = false, append = false;

4
backends/intersynth/intersynth.cc
View File

@ -46,7 +46,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
struct IntersynthBackend : public Backend {
IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -71,7 +71,7 @@ struct IntersynthBackend : public Backend {
log("http://www.clifford.at/intersynth/\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing INTERSYNTH backend.\n");
log_push();

8
backends/json/json.cc
View File

@ -294,7 +294,7 @@ struct JsonWriter
struct JsonBackend : public Backend {
JsonBackend() : Backend("json", "write design to a JSON file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -530,7 +530,7 @@ struct JsonBackend : public Backend {
log("format. A program processing this format must ignore all unknown fields.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool aig_mode = false;
bool compat_int_mode = false;
@ -559,7 +559,7 @@ struct JsonBackend : public Backend {
struct JsonPass : public Pass {
JsonPass() : Pass("json", "write design in JSON format") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -580,7 +580,7 @@ struct JsonPass : public Pass {
log("See 'help write_json' for a description of the JSON format used.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool aig_mode = false;

8
backends/protobuf/protobuf.cc
View File

@ -231,7 +231,7 @@ struct ProtobufDesignSerializer
struct ProtobufBackend : public Backend {
ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend {
log("Yosys source code distribution.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool aig_mode = false;
bool text_mode = false;
@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend {
struct ProtobufPass : public Pass {
ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -307,7 +307,7 @@ struct ProtobufPass : public Pass {
log("Yosys source code distribution.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool aig_mode = false;

4
backends/simplec/simplec.cc
View File

@ -744,7 +744,7 @@ struct SimplecWorker
struct SimplecBackend : public Backend {
SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -763,7 +763,7 @@ struct SimplecBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
reserved_cids.clear();
id2cid.clear();

4
backends/smt2/smt2.cc
View File

@ -1280,7 +1280,7 @@ struct Smt2Worker
struct Smt2Backend : public Backend {
Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1436,7 +1436,7 @@ struct Smt2Backend : public Backend {
log("from non-zero to zero in the test design.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::ifstream template_f;
bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false;

4
backends/smv/smv.cc
View File

@ -702,7 +702,7 @@ struct SmvWorker
struct SmvBackend : public Backend {
SmvBackend() : Backend("smv", "write design to SMV file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -720,7 +720,7 @@ struct SmvBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::ifstream template_f;
bool verbose = false;

4
backends/spice/spice.cc
View File

@ -130,7 +130,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
struct SpiceBackend : public Backend {
SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -159,7 +159,7 @@ struct SpiceBackend : public Backend {
log(" set the specified module as design top module\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::string top_module_name;
RTLIL::Module *top_module = NULL;

4
backends/table/table.cc
View File

@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TableBackend : public Backend {
TableBackend() : Backend("table", "write design as connectivity table") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -48,7 +48,7 @@ struct TableBackend : public Backend {
log("module inputs and outputs are output using cell type and port '-' and with\n");
log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing TABLE backend.\n");

4
backends/verilog/verilog_backend.cc
View File

@ -1873,7 +1873,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
struct VerilogBackend : public Backend {
VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1953,7 +1953,7 @@ struct VerilogBackend : public Backend {
log("this command is called on a design with RTLIL processes.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing Verilog backend.\n");

2
examples/cxx-api/evaldemo.cc
View File

@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass
{
EvalDemoPass() : Pass("evaldemo") { }
void execute(vector<string>, Design *design) YS_OVERRIDE
void execute(vector<string>, Design *design) override
{
Module *module = design->top_module();

4
frontends/aiger/aigerparse.cc
View File

@ -970,7 +970,7 @@ void AigerReader::post_process()
struct AigerFrontend : public Frontend {
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -996,7 +996,7 @@ struct AigerFrontend : public Frontend {
log(" read XAIGER extensions\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing AIGER frontend.\n");

10
frontends/ast/ast.h
View File

@ -322,12 +322,12 @@ namespace AST
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
~AstModule() YS_OVERRIDE;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) YS_OVERRIDE;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE;
~AstModule() override;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);
void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE;
RTLIL::Module *clone() const YS_OVERRIDE;
void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
RTLIL::Module *clone() const override;
void loadconfig() const;
};

4
frontends/blif/blifparse.cc
View File

@ -586,7 +586,7 @@ error_with_reason:
struct BlifFrontend : public Frontend {
BlifFrontend() : Frontend("blif", "read BLIF file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -602,7 +602,7 @@ struct BlifFrontend : public Frontend {
log(" multi-bit port 'name'.\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool sop_mode = false;
bool wideports = false;

4
frontends/ilang/ilang_frontend.cc
View File

@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN
struct IlangFrontend : public Frontend {
IlangFrontend() : Frontend("ilang", "read modules from ilang file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -56,7 +56,7 @@ struct IlangFrontend : public Frontend {
log(" only create empty blackbox modules\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
ILANG_FRONTEND::flag_nooverwrite = false;
ILANG_FRONTEND::flag_overwrite = false;

4
frontends/json/jsonparse.cc
View File

@ -535,7 +535,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
struct JsonFrontend : public Frontend {
JsonFrontend() : Frontend("json", "read JSON file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -545,7 +545,7 @@ struct JsonFrontend : public Frontend {
log("for a description of the file format.\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing JSON frontend.\n");

4
frontends/liberty/liberty.cc
View File

@ -453,7 +453,7 @@ void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map,
struct LibertyFrontend : public Frontend {
LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -486,7 +486,7 @@ struct LibertyFrontend : public Frontend {
log(" set the specified attribute (to the value 1) on all loaded modules\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_lib = false;
bool flag_nooverwrite = false;

16
frontends/rpc/rpc_frontend.cc
View File

@ -157,7 +157,7 @@ struct RpcServer {
struct RpcModule : RTLIL::Module {
std::shared_ptr<RpcServer> server;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) YS_OVERRIDE {
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
std::string stripped_name = name.str();
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
@ -229,7 +229,7 @@ struct RpcModule : RTLIL::Module {
return derived_name;
}
RTLIL::Module *clone() const YS_OVERRIDE {
RTLIL::Module *clone() const override {
RpcModule *new_mod = new RpcModule;
new_mod->server = server;
cloneInto(new_mod);
@ -250,7 +250,7 @@ struct HandleRpcServer : RpcServer {
HandleRpcServer(const std::string &name, HANDLE hsend, HANDLE hrecv)
: RpcServer(name), hsend(hsend), hrecv(hrecv) { }
void write(const std::string &data) YS_OVERRIDE {
void write(const std::string &data) override {
log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1);
ssize_t offset = 0;
do {
@ -261,7 +261,7 @@ struct HandleRpcServer : RpcServer {
} while(offset < (ssize_t)data.length());
}
std::string read() YS_OVERRIDE {
std::string read() override {
std::string data;
ssize_t offset = 0;
while (data.length() == 0 || data[data.length() - 1] != '\n') {
@ -304,7 +304,7 @@ struct FdRpcServer : RpcServer {
log_cmd_error("RPC frontend terminated unexpectedly\n");
}
void write(const std::string &data) YS_OVERRIDE {
void write(const std::string &data) override {
log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1);
ssize_t offset = 0;
do {
@ -316,7 +316,7 @@ struct FdRpcServer : RpcServer {
} while(offset < (ssize_t)data.length());
}
std::string read() YS_OVERRIDE {
std::string read() override {
std::string data;
ssize_t offset = 0;
while (data.length() == 0 || data[data.length() - 1] != '\n') {
@ -346,7 +346,7 @@ struct FdRpcServer : RpcServer {
// RpcFrontend does not inherit from Frontend since it does not read files.
struct RpcFrontend : public Pass {
RpcFrontend() : Pass("connect_rpc", "connect to RPC frontend") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -390,7 +390,7 @@ struct RpcFrontend : public Pass {
log(" so the response should be the same whenever the same set of parameters\n");
log(" is provided.\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Connecting to RPC frontend.\n");

10
frontends/verific/verific.cc
View File

@ -2008,7 +2008,7 @@ bool check_noverific_env()
struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -2147,7 +2147,7 @@ struct VerificPass : public Pass {
log("\n");
}
#ifdef YOSYS_ENABLE_VERIFIC
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
static bool set_verific_global_flags = true;
@ -2582,7 +2582,7 @@ struct VerificPass : public Pass {
}
#else /* YOSYS_ENABLE_VERIFIC */
void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
void execute(std::vector<std::string>, RTLIL::Design *) override {
log_cmd_error("This version of Yosys is built without Verific support.\n"
"\n"
"Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
@ -2596,7 +2596,7 @@ struct VerificPass : public Pass {
struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -2637,7 +2637,7 @@ struct ReadPass : public Pass {
log("Verific support. The default is to use Verific if it is available.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
#ifdef YOSYS_ENABLE_VERIFIC
static bool verific_available = !check_noverific_env();

12
frontends/verilog/verilog_frontend.cc
View File

@ -67,7 +67,7 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -232,7 +232,7 @@ struct VerilogFrontend : public Frontend {
log("supported by the Yosys Verilog front-end.\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false;
@ -503,7 +503,7 @@ struct VerilogFrontend : public Frontend {
struct VerilogDefaults : public Pass {
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -524,7 +524,7 @@ struct VerilogDefaults : public Pass {
log("not imply -clear.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() < 2)
cmd_error(args, 1, "Missing argument.");
@ -561,7 +561,7 @@ struct VerilogDefaults : public Pass {
struct VerilogDefines : public Pass {
VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -583,7 +583,7 @@ struct VerilogDefines : public Pass {
log(" list currently defined preprocessor symbols\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
kernel/celledges.h
View File

@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db;
FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[from_sigbit].insert(to_sigbit);
@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db;
RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[to_sigbit].insert(from_sigbit);

8
kernel/modtools.h
View File

@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor
#endif
}
void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log_assert(module == cell->module);
@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
port_add(cell, port, sig);
}
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) override
{
log_assert(module == mod);
@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
}
}
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) override
{
log_assert(module == mod);
auto_reload_module = true;
}
void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) override
{
log_assert(module == mod);
auto_reload_module = true;

10
kernel/register.cc
View File

@ -753,7 +753,7 @@ static struct CellHelpMessages {
struct HelpPass : public Pass {
HelpPass() : Pass("help", "display help messages") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" help ................ list all commands\n");
@ -822,7 +822,7 @@ struct HelpPass : public Pass {
fclose(f);
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() == 1) {
log("\n");
@ -926,7 +926,7 @@ struct HelpPass : public Pass {
struct EchoPass : public Pass {
EchoPass() : Pass("echo", "turning echoing back of commands on and off") { }
void help() YS_OVERRIDE
void help() override
{
log("\n");
log(" echo on\n");
@ -939,7 +939,7 @@ struct EchoPass : public Pass {
log("Do not print all commands to log before executing them. (default)\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() > 2)
cmd_error(args, 2, "Unexpected argument.");
@ -964,7 +964,7 @@ struct MinisatSatSolver : public SatSolver {
MinisatSatSolver() : SatSolver("minisat") {
yosys_satsolver = this;
}
ezSAT *create() YS_OVERRIDE {
ezSAT *create() override {
return new ezMiniSAT();
}
} MinisatSatSolver;

12
kernel/register.h
View File

@ -97,9 +97,9 @@ struct Frontend : Pass
std::string frontend_name;
Frontend(std::string name, std::string short_help = "** document me **");
void run_register() YS_OVERRIDE;
~Frontend() YS_OVERRIDE;
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
void run_register() override;
~Frontend() override;
void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
static std::vector<std::string> next_args;
@ -113,9 +113,9 @@ struct Backend : Pass
{
std::string backend_name;
Backend(std::string name, std::string short_help = "** document me **");
void run_register() YS_OVERRIDE;
~Backend() YS_OVERRIDE;
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
void run_register() override;
~Backend() override;
void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);

16
kernel/yosys.cc
View File

@ -713,7 +713,7 @@ extern Tcl_Interp *yosys_get_tcl_interp()
struct TclPass : public Pass {
TclPass() : Pass("tcl", "execute a TCL script file") { }
void help() YS_OVERRIDE {
void help() override {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" tcl <filename> [args]\n");
@ -730,7 +730,7 @@ struct TclPass : public Pass {
log("the standard $argc and $argv variables.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *) YS_OVERRIDE {
void execute(std::vector<std::string> args, RTLIL::Design *) override {
if (args.size() < 2)
log_cmd_error("Missing script file.\n");
@ -1220,7 +1220,7 @@ void shell(RTLIL::Design *design)
struct ShellPass : public Pass {
ShellPass() : Pass("shell", "enter interactive command mode") { }
void help() YS_OVERRIDE {
void help() override {
log("\n");
log(" shell\n");
log("\n");
@ -1252,7 +1252,7 @@ struct ShellPass : public Pass {
log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
extra_args(args, 1, design, false);
shell(design);
}
@ -1261,7 +1261,7 @@ struct ShellPass : public Pass {
#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
struct HistoryPass : public Pass {
HistoryPass() : Pass("history", "show last interactive commands") { }
void help() YS_OVERRIDE {
void help() override {
log("\n");
log(" history\n");
log("\n");
@ -1270,7 +1270,7 @@ struct HistoryPass : public Pass {
log("from executed scripts.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
extra_args(args, 1, design, false);
#ifdef YOSYS_ENABLE_READLINE
for(HIST_ENTRY **list = history_list(); *list != NULL; list++)
@ -1285,7 +1285,7 @@ struct HistoryPass : public Pass {
struct ScriptCmdPass : public Pass {
ScriptCmdPass() : Pass("script", "execute commands from file or wire") { }
void help() YS_OVERRIDE {
void help() override {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" script <filename> [<from_label>:<to_label>]\n");
@ -1308,7 +1308,7 @@ struct ScriptCmdPass : public Pass {
log("'-module' mode can be exited by using the 'cd' command.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool scriptwire = false;

8
kernel/yosys.h
View File

@ -136,14 +136,6 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
#define YOSYS_NAMESPACE_PREFIX Yosys::
#define USING_YOSYS_NAMESPACE using namespace Yosys;
#if __cplusplus >= 201103L
# define YS_OVERRIDE override
# define YS_FINAL final
#else
# define YS_OVERRIDE
# define YS_FINAL
#endif
#if defined(__GNUC__) || defined(__clang__)
# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
# define YS_NORETURN

2
manual/CHAPTER_Prog/stubnets.cc
View File

@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// each pass contains a singleton object that is derived from Pass
struct StubnetsPass : public Pass {
StubnetsPass() : Pass("stubnets") { }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
// variables to mirror information from passed options
bool report_bits = 0;

6
manual/PRESENTATION_Prog/my_cmd.cc
View File

@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MyPass : public Pass {
MyPass() : Pass("my_cmd", "just a simple test") { }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log("Arguments to my_cmd:\n");
for (auto &arg : args)
@ -22,7 +22,7 @@ struct MyPass : public Pass {
struct Test1Pass : public Pass {
Test1Pass() : Pass("test1", "creating the absval module") { }
void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string>, RTLIL::Design *design) override
{
if (design->has("\\absval") != 0)
log_error("A module with the name absval already exists!\n");
@ -49,7 +49,7 @@ struct Test1Pass : public Pass {
struct Test2Pass : public Pass {
Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string>, RTLIL::Design *design) override
{
if (design->selection_stack.back().empty())
log_cmd_error("This command can't operator on an empty selection!\n");

4
passes/cmds/add.cc
View File

@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
struct AddPass : public Pass {
AddPass() : Pass("add", "add objects to the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -150,7 +150,7 @@ struct AddPass : public Pass {
log("Add module[s] with the specified name[s].\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string command;
std::string arg_name;

4
passes/cmds/autoname.cc
View File

@ -92,7 +92,7 @@ int autoname_worker(Module *module)
struct AutonamePass : public Pass {
AutonamePass() : Pass("autoname", "automatically assign names to objects") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -102,7 +102,7 @@ struct AutonamePass : public Pass {
log("with $-prefix).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

4
passes/cmds/blackbox.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass {
BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -34,7 +34,7 @@ struct BlackboxPass : public Pass {
log("module attribute).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

4
passes/cmds/bugpoint.cc
View File

@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BugpointPass : public Pass {
BugpointPass() : Pass("bugpoint", "minimize testcases") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -313,7 +313,7 @@ struct BugpointPass : public Pass {
return nullptr;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string yosys_cmd = "yosys", script, grep;
bool fast = false, clean = false;

4
passes/cmds/check.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CheckPass : public Pass {
CheckPass() : Pass("check", "check for obvious problems in the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -61,7 +61,7 @@ struct CheckPass : public Pass {
log(" Produce a runtime error if any problems are found in the current design.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int counter = 0;
bool noinit = false;

4
passes/cmds/chformal.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChformalPass : public Pass {
ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -62,7 +62,7 @@ struct ChformalPass : public Pass {
log(" change the roles of cells as indicated. these options can be combined\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool assert2assume = false;
bool assume2assert = false;

4
passes/cmds/chtype.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -40,7 +40,7 @@ struct ChtypePass : public Pass {
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
IdString set_type;
dict<IdString, IdString> map_types;

4
passes/cmds/connect.cc
View File

@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
struct ConnectPass : public Pass {
ConnectPass() : Pass("connect", "create or remove connections") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
log("This command does not operate on module with processes.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {

4
passes/cmds/connwrappers.cc
View File

@ -143,7 +143,7 @@ struct ConnwrappersWorker
struct ConnwrappersPass : public Pass {
ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -165,7 +165,7 @@ struct ConnwrappersPass : public Pass {
log("The options -signed, -unsigned, and -port can be specified multiple times.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ConnwrappersWorker worker;

4
passes/cmds/copy.cc
View File

@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CopyPass : public Pass {
CopyPass() : Pass("copy", "copy modules in the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -36,7 +36,7 @@ struct CopyPass : public Pass {
log("by this command.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (args.size() != 3)
log_cmd_error("Invalid number of arguments!\n");

4
passes/cmds/cover.cc
View File

@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -83,7 +83,7 @@ struct CoverPass : public Pass {
log("Coverage counters are only available in Yosys for Linux.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<FILE*> out_files;
std::vector<std::string> patterns;

4
passes/cmds/delete.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -40,7 +40,7 @@ struct DeletePass : public Pass {
log("selected wires, thus 'deleting' module ports.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_input = false;
bool flag_output = false;

6
passes/cmds/design.cc
View File

@ -28,7 +28,7 @@ std::vector<RTLIL::Design*> pushed_designs;
struct DesignPass : public Pass {
DesignPass() : Pass("design", "save, restore and reset current design") { }
~DesignPass() YS_OVERRIDE {
~DesignPass() override {
for (auto &it : saved_designs)
delete it.second;
saved_designs.clear();
@ -36,7 +36,7 @@ struct DesignPass : public Pass {
delete it;
pushed_designs.clear();
}
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -105,7 +105,7 @@ struct DesignPass : public Pass {
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool got_mode = false;
bool reset_mode = false;

4
passes/cmds/edgetypes.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EdgetypePass : public Pass {
EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -35,7 +35,7 @@ struct EdgetypePass : public Pass {
log("is a 4-tuple of source and sink cell type and port name.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
passes/cmds/exec.cc
View File

@ -38,7 +38,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ExecPass : public Pass {
ExecPass() : Pass("exec", "execute commands in the operating system shell") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -71,7 +71,7 @@ struct ExecPass : public Pass {
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string cmd = "";
char buf[1024] = {};

4
passes/cmds/logcmd.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct LogPass : public Pass {
LogPass() : Pass("log", "print text and log files") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -52,7 +52,7 @@ struct LogPass : public Pass {
log(" do not append a newline\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design*) override
{
size_t argidx;
bool to_stdout = false;

4
passes/cmds/logger.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct LoggerPass : public Pass {
LoggerPass() : Pass("logger", "set logger properties") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -66,7 +66,7 @@ struct LoggerPass : public Pass {
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design * design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design * design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

4
passes/cmds/ltp.cc
View File

@ -141,7 +141,7 @@ struct LtpWorker
struct LtpPass : public Pass {
LtpPass() : Pass("ltp", "print longest topological path") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -154,7 +154,7 @@ struct LtpPass : public Pass {
log(" automatically exclude FF cell types\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool noff = false;

4
passes/cmds/plugin.cc
View File

@ -99,7 +99,7 @@ void load_plugin(std::string, std::vector<std::string>)
struct PluginPass : public Pass {
PluginPass() : Pass("plugin", "load and list loaded plugins") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -117,7 +117,7 @@ struct PluginPass : public Pass {
log(" List loaded plugins\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string plugin_filename;
std::vector<std::string> plugin_aliases;

4
passes/cmds/portlist.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct PortlistPass : public Pass {
PortlistPass() : Pass("portlist", "list (top-level) ports") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -39,7 +39,7 @@ struct PortlistPass : public Pass {
log(" print verilog blackbox module definitions instead of port lists\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool m_mode = false;

4
passes/cmds/printattrs.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct PrintAttrsPass : public Pass {
PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -48,7 +48,7 @@ struct PrintAttrsPass : public Pass {
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = 1;
extra_args(args, argidx, design);

4
passes/cmds/qwp.cc
View File

@ -778,7 +778,7 @@ struct QwpWorker
struct QwpPass : public Pass {
QwpPass() : Pass("qwp", "quadratic wirelength placer") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -808,7 +808,7 @@ struct QwpPass : public Pass {
log("dense matrix operations. It is only a toy-placer for small circuits.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
QwpConfig config;
xorshift32_state = 123456789;

4
passes/cmds/rename.cc
View File

@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
struct RenamePass : public Pass {
RenamePass() : Pass("rename", "rename object in the design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -152,7 +152,7 @@ struct RenamePass : public Pass {
log("Rename top module.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_src = false;

4
passes/cmds/scatter.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -41,7 +41,7 @@ struct ScatterPass : public Pass {
log("Use the opt_clean command to get rid of the additional nets.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
CellTypes ct(design);
extra_args(args, 1, design);

4
passes/cmds/scc.cc
View File

@ -218,7 +218,7 @@ struct SccWorker
struct SccPass : public Pass {
SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -255,7 +255,7 @@ struct SccPass : public Pass {
log(" that are part of a found logic loop\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::map<std::string, std::string> setAttr;
bool allCellTypes = false;

4
passes/cmds/scratchpad.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ScratchpadPass : public Pass {
ScratchpadPass() : Pass("scratchpad", "get/set values in the scratchpad") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -63,7 +63,7 @@ struct ScratchpadPass : public Pass {
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

12
passes/cmds/select.cc
View File

@ -1021,7 +1021,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SelectPass : public Pass {
SelectPass() : Pass("select", "modify and view the list of selected objects") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1250,7 +1250,7 @@ struct SelectPass : public Pass {
log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool add_mode = false;
bool del_mode = false;
@ -1587,7 +1587,7 @@ struct SelectPass : public Pass {
struct CdPass : public Pass {
CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1613,7 +1613,7 @@ struct CdPass : public Pass {
log("This is just a shortcut for 'select -clear'.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (args.size() != 1 && args.size() != 2)
log_cmd_error("Invalid number of arguments.\n");
@ -1693,7 +1693,7 @@ static void log_matches(const char *title, Module *module, const T &list)
struct LsPass : public Pass {
LsPass() : Pass("ls", "list modules or objects in modules") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1704,7 +1704,7 @@ struct LsPass : public Pass {
log("When an active module is selected, this prints a list of objects in the module.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = 1;
extra_args(args, argidx, design);

16
passes/cmds/setattr.cc
View File

@ -56,7 +56,7 @@ static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::v
struct SetattrPass : public Pass {
SetattrPass() : Pass("setattr", "set/unset attributes on objects") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -69,7 +69,7 @@ struct SetattrPass : public Pass {
log("instead of objects within modules.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<setunset_t> setunset_list;
bool flag_mod = false;
@ -128,7 +128,7 @@ struct SetattrPass : public Pass {
struct WbflipPass : public Pass {
WbflipPass() : Pass("wbflip", "flip the whitebox attribute") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -138,7 +138,7 @@ struct WbflipPass : public Pass {
log("vice-versa. Blackbox cells are not effected by this command.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -167,7 +167,7 @@ struct WbflipPass : public Pass {
struct SetparamPass : public Pass {
SetparamPass() : Pass("setparam", "set/unset parameters on objects") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -179,7 +179,7 @@ struct SetparamPass : public Pass {
log("The -type option can be used to change the cell type of the selected cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
vector<setunset_t> setunset_list;
string new_cell_type;
@ -219,7 +219,7 @@ struct SetparamPass : public Pass {
struct ChparamPass : public Pass {
ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -234,7 +234,7 @@ struct ChparamPass : public Pass {
log("List the available parameters of the selected modules.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<setunset_t> setunset_list;
dict<RTLIL::IdString, RTLIL::Const> new_parameters;

4
passes/cmds/setundef.cc
View File

@ -107,7 +107,7 @@ struct SetundefWorker
struct SetundefPass : public Pass {
SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -147,7 +147,7 @@ struct SetundefPass : public Pass {
log(" replace undef in cell parameters\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int got_value = 0;
bool undriven_mode = false;

4
passes/cmds/show.cc
View File

@ -587,7 +587,7 @@ struct ShowWorker
struct ShowPass : public Pass {
ShowPass() : Pass("show", "generate schematics using graphviz") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -674,7 +674,7 @@ struct ShowPass : public Pass {
log("the 'show' command is executed.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Generating Graphviz representation of design.\n");
log_push();

4
passes/cmds/splice.cc
View File

@ -246,7 +246,7 @@ struct SpliceWorker
struct SplicePass : public Pass {
SplicePass() : Pass("splice", "create explicit splicing cells") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -287,7 +287,7 @@ struct SplicePass : public Pass {
log("by selected wires are rewired.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool sel_by_cell = false;
bool sel_by_wire = false;

4
passes/cmds/splitnets.cc
View File

@ -95,7 +95,7 @@ struct SplitnetsWorker
struct SplitnetsPass : public Pass {
SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass {
log(" and split nets so that no driver drives only part of a net.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_ports = false;
bool flag_driver = false;

4
passes/cmds/stat.cc
View File

@ -282,7 +282,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
struct StatPass : public Pass {
StatPass() : Pass("stat", "print some statistics") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -308,7 +308,7 @@ struct StatPass : public Pass {
log(" e.g. $add_8 for an 8 bit wide $add cell.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Printing statistics.\n");

4
passes/cmds/tee.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TeePass : public Pass {
TeePass() : Pass("tee", "redirect command output to file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -49,7 +49,7 @@ struct TeePass : public Pass {
log(" Add/subtract INT from the -v setting for this command.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<FILE*> backup_log_files, files_to_close;
std::vector<std::ostream*> backup_log_streams;

4
passes/cmds/torder.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TorderPass : public Pass {
TorderPass() : Pass("torder", "print cells in topological order") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -43,7 +43,7 @@ struct TorderPass : public Pass {
log(" are not used in topological sorting. this option deactivates that.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool noautostop = false;
dict<IdString, pool<IdString>> stop_db;

20
passes/cmds/trace.cc
View File

@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN
struct TraceMonitor : public RTLIL::Monitor
{
void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
void notify_module_add(RTLIL::Module *module) override
{
log("#TRACE# Module add: %s\n", log_id(module));
}
void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
void notify_module_del(RTLIL::Module *module) override
{
log("#TRACE# Module delete: %s\n", log_id(module));
}
void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
}
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
{
log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
{
log("#TRACE# New connections in module %s:\n", log_id(module));
for (auto &sigsig : sigsig_vec)
log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
void notify_blackout(RTLIL::Module *module) override
{
log("#TRACE# Blackout in module %s:\n", log_id(module));
}
@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor
struct TracePass : public Pass {
TracePass() : Pass("trace", "redirect command output to file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -70,7 +70,7 @@ struct TracePass : public Pass {
log("the design in real time.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -96,7 +96,7 @@ struct TracePass : public Pass {
struct DebugPass : public Pass {
DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -105,7 +105,7 @@ struct DebugPass : public Pass {
log("Execute the specified command with debug log messages enabled\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

4
passes/cmds/write_file.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct WriteFileFrontend : public Frontend {
WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend {
log(" EOT\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) override
{
bool append_mode = false;
std::string output_filename;

4
passes/equiv/equiv_add.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivAddPass : public Pass {
EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -39,7 +39,7 @@ struct EquivAddPass : public Pass {
log("This command adds $equiv cells for the ports of the specified cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
bool try_mode = false;

4
passes/equiv/equiv_induct.cc
View File

@ -162,7 +162,7 @@ struct EquivInductWorker
struct EquivInductPass : public Pass {
EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
log("after reset.\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
int success_counter = 0;
bool model_undef = false;

4
passes/equiv/equiv_make.cc
View File

@ -466,7 +466,7 @@ struct EquivMakeWorker
struct EquivMakePass : public Pass {
EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -491,7 +491,7 @@ struct EquivMakePass : public Pass {
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
EquivMakeWorker worker;
worker.ct.setup(design);

4
passes/equiv/equiv_mark.cc
View File

@ -204,7 +204,7 @@ struct EquivMarkWorker
struct EquivMarkPass : public Pass {
EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass {
log("wires and cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
log_header(design, "Executing EQUIV_MARK pass.\n");

4
passes/equiv/equiv_miter.cc
View File

@ -261,7 +261,7 @@ struct EquivMiterWorker
struct EquivMiterPass : public Pass {
EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass {
log(" Create compare logic that handles undefs correctly\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
EquivMiterWorker worker;
worker.ct.setup(design);

8
passes/equiv/equiv_opt.cc
View File

@ -26,7 +26,7 @@ struct EquivOptPass:public ScriptPass
{
EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -68,7 +68,7 @@ struct EquivOptPass:public ScriptPass
std::string command, techmap_opts, make_opts;
bool assert, undef, multiclock, async2sync;
void clear_flags() YS_OVERRIDE
void clear_flags() override
{
command = "";
techmap_opts = "";
@ -79,7 +79,7 @@ struct EquivOptPass:public ScriptPass
async2sync = false;
}
void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
void execute(std::vector < std::string > args, RTLIL::Design * design) override
{
string run_from, run_to;
clear_flags();
@ -148,7 +148,7 @@ struct EquivOptPass:public ScriptPass
log_pop();
}
void script() YS_OVERRIDE
void script() override
{
if (check_label("run_pass")) {
run("hierarchy -auto-top");

4
passes/equiv/equiv_purge.cc
View File

@ -176,7 +176,7 @@ struct EquivPurgeWorker
struct EquivPurgePass : public Pass {
EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass {
log("ports as needed.\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
log_header(design, "Executing EQUIV_PURGE pass.\n");

4
passes/equiv/equiv_remove.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivRemovePass : public Pass {
EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass {
log(" keep gate circuit\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
bool mode_gold = false;
bool mode_gate = false;

4
passes/equiv/equiv_simple.cc
View File

@ -273,7 +273,7 @@ struct EquivSimpleWorker
struct EquivSimplePass : public Pass {
EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass {
log(" the max. number of time steps to be considered (default = 1)\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
int success_counter = 0;

4
passes/equiv/equiv_status.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivStatusPass : public Pass {
EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass {
log(" produce an error if any unproven $equiv cell is found\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
bool assert_mode = false;
int unproven_count = 0;

4
passes/equiv/equiv_struct.cc
View File

@ -283,7 +283,7 @@ struct EquivStructWorker
struct EquivStructPass : public Pass {
EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
log(" maximum number of iterations to run before aborting\n");
log("\n");
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, Design *design) override
{
pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false;

4
passes/fsm/fsm.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmPass : public Pass {
FsmPass() : Pass("fsm", "extract and optimize finite state machines") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -68,7 +68,7 @@ struct FsmPass : public Pass {
log(" passed through to fsm_recode pass\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nomap = false;
bool flag_norecode = false;

4
passes/fsm/fsm_detect.cc
View File

@ -257,7 +257,7 @@ static void detect_fsm(RTLIL::Wire *wire)
struct FsmDetectPass : public Pass {
FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -273,7 +273,7 @@ struct FsmDetectPass : public Pass {
log("'fsm_encoding' attribute to \"none\".\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
extra_args(args, 1, design);

4
passes/fsm/fsm_expand.cc
View File

@ -265,7 +265,7 @@ struct FsmExpand
struct FsmExpandPass : public Pass {
FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass {
log("word-wide cells. Call with -full to consider all cells for merging.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool full_mode = false;

4
passes/fsm/fsm_export.cc
View File

@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
*/
struct FsmExportPass : public Pass {
FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -143,7 +143,7 @@ struct FsmExportPass : public Pass {
log(" use binary state encoding as state names instead of s0, s1, ...\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
std::string arg;

4
passes/fsm/fsm_extract.cc
View File

@ -401,7 +401,7 @@ static void extract_fsm(RTLIL::Wire *wire)
struct FsmExtractPass : public Pass {
FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass {
log("'opt_clean' pass to eliminate this signal.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);

4
passes/fsm/fsm_info.cc
View File

@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmInfoPass : public Pass {
FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass {
log("pass so that this information is included in the synthesis log file.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);

4
passes/fsm/fsm_map.cc
View File

@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
struct FsmMapPass : public Pass {
FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -331,7 +331,7 @@ struct FsmMapPass : public Pass {
log("This pass translates FSM cells to flip-flops and logic.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);

4
passes/fsm/fsm_opt.cc
View File

@ -324,7 +324,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmOptPass : public Pass {
FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -335,7 +335,7 @@ struct FsmOptPass : public Pass {
log("combination with the 'opt_clean' pass (see also 'help fsm').\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);

4
passes/fsm/fsm_recode.cc
View File

@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
struct FsmRecodePass : public Pass {
FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass {
log(" .map <old_bitpattern> <new_bitpattern>\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
FILE *fm_set_fsm_file = NULL;
FILE *encfile = NULL;

4
passes/hierarchy/hierarchy.cc
View File

@ -558,7 +558,7 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri
struct HierarchyPass : public Pass {
HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -639,7 +639,7 @@ struct HierarchyPass : public Pass {
log("in the current design.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");

4
passes/hierarchy/submod.cc
View File

@ -319,7 +319,7 @@ struct SubmodWorker
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -351,7 +351,7 @@ struct SubmodPass : public Pass {
log(" original module with original public names.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();

4
passes/hierarchy/uniquify.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct UniquifyPass : public Pass {
UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -41,7 +41,7 @@ struct UniquifyPass : public Pass {
log("attribute set (the 'top' module is unique implicitly).\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");

4
passes/memory/memory.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MemoryPass : public Pass {
MemoryPass() : Pass("memory", "translate memories to basic cells") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -49,7 +49,7 @@ struct MemoryPass : public Pass {
log("or multiport memory blocks if called with the -nomap option.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nomap = false;
bool flag_nordff = false;

4
passes/memory/memory_bram.cc
View File

@ -1265,7 +1265,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
struct MemoryBramPass : public Pass {
MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -1367,7 +1367,7 @@ struct MemoryBramPass : public Pass {
log("the data bits to accommodate the enable pattern of port A.\n");
log("\n");
}
void execute(vector<string> args, Design *design) YS_OVERRIDE
void execute(vector<string> args, Design *design) override
{
rules_t rules;

4
passes/memory/memory_collect.cc
View File

@ -245,7 +245,7 @@ static void handle_module(Design *design, Module *module)
struct MemoryCollectPass : public Pass {
MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -255,7 +255,7 @@ struct MemoryCollectPass : public Pass {
log("memory cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())

4
passes/memory/memory_dff.cc
View File

@ -291,7 +291,7 @@ struct MemoryDffWorker
struct MemoryDffPass : public Pass {
MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -305,7 +305,7 @@ struct MemoryDffPass : public Pass {
log(" do not merge registers on read ports\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_wr_only = false;

4
passes/memory/memory_map.cc
View File

@ -403,7 +403,7 @@ struct MemoryMapWorker
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
void help() YS_OVERRIDE
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -425,7 +425,7 @@ struct MemoryMapPass : public Pass {
log(" for -attr, ignore case of <value>.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool attr_icase = false;
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;

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