riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

xaiger: do not promote output wires

This commit is contained in:
Eddie Hung 2019-11-26 19:03:02 -08:00
parent 0466c48533
commit 7136cee6b4
1 changed files with 0 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
backends/aiger/xaiger.cc
View File

@ -153,11 +153,6 @@ struct XAigerWriter
if (wire->port_input) if (wire->port_input)
sigmap.add(wire); sigmap.add(wire);
// promote output wires
for (auto wire : module->wires())
if (wire->port_output)
sigmap.add(wire);
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
bool keep = wire->attributes.count("\\keep"); bool keep = wire->attributes.count("\\keep");