mirror of https://github.com/YosysHQ/yosys.git
abstract: no more bufnorm, -value has bit selection consistent with -state, -init temporarily gutted
This commit is contained in:
Emil J. Tywoniak
parent
355f5e3740
commit
6ffc12389f
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@ -100,71 +100,78 @@ unsigned int abstract_state(Module* mod, EnableLogic enable) {
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return changed;
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}
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struct AbstractPortCtx {
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Module* mod;
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SigMap sigmap;
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pool<std::pair<Cell*, IdString>> outs;
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};
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void collect_selected_ports(AbstractPortCtx& ctx) {
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for (Cell* cell : ctx.mod->cells()) {
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for (auto& conn : cell->connections()) {
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// we bufnorm
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log_assert(conn.second.is_wire() || conn.second.is_fully_const());
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if (conn.second.is_wire() && cell->output(conn.first))
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if (ctx.mod->selected(cell) || ctx.mod->selected(conn.second.as_wire()))
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ctx.outs.insert(std::make_pair(cell, conn.first));
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}
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}
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}
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unsigned int abstract_value(Module* mod, EnableLogic enable) {
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AbstractPortCtx ctx {mod, SigMap(mod), {}};
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collect_selected_ports(ctx);
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SigMap sigmap(mod);
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pool<SigBit> selected_representatives = gather_selected_reps(mod, sigmap);
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unsigned int changed = 0;
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for (auto [cell, port] : ctx.outs) {
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SigSpec sig = cell->getPort(port);
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log_assert(sig.is_wire());
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Wire* original = mod->addWire(NEW_ID, sig.size());
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cell->setPort(port, original);
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auto anyseq = mod->Anyseq(NEW_ID, sig.size());
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// This code differs from abstract_state
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// in that we reuse the original signal as the mux output,
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// not input
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = original;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = original;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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sig);
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changed++;
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std::vector<Cell*> cells_snapshot = mod->cells();
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for (auto cell : cells_snapshot) {
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for (auto conn : cell->connections())
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if (cell->output(conn.first)) {
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std::set<int> offsets_to_abstract;
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for (int i = 0; i < conn.second.size(); i++) {
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if (selected_representatives.count(sigmap(conn.second[i]))) {
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offsets_to_abstract.insert(i);
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}
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}
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if (offsets_to_abstract.empty())
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continue;
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auto anyseq = mod->Anyseq(NEW_ID, offsets_to_abstract.size());
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Wire* to_abstract = mod->addWire(NEW_ID, offsets_to_abstract.size());
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SigSpec mux_input;
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SigSpec mux_output;
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SigSpec new_port = conn.second;
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int to_abstract_idx = 0;
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for (int port_idx = 0; port_idx < conn.second.size(); port_idx++) {
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if (offsets_to_abstract.count(port_idx)) {
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log_debug("bit %d: abstracted\n", port_idx);
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mux_output.append(conn.second[port_idx]);
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SigBit in_bit {to_abstract, to_abstract_idx};
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new_port.replace(port_idx, in_bit);
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conn.second[port_idx] = {mod->addWire(NEW_ID, 1), 0};
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mux_input.append(in_bit);
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log_assert(to_abstract_idx < to_abstract->width);
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to_abstract_idx++;
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}
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}
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cell->setPort(conn.first, new_port);
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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mux_output);
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changed++;
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}
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}
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return changed;
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}
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unsigned int abstract_init(Module* mod) {
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AbstractPortCtx ctx {mod, SigMap(mod), {}};
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collect_selected_ports(ctx);
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// AbstractPortCtx ctx {mod, SigMap(mod), {}};
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// collect_selected_ports(ctx);
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unsigned int changed = 0;
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for (auto [cell, port] : ctx.outs) {
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SigSpec sig = cell->getPort(port);
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log_assert(sig.is_wire());
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if (!sig.as_wire()->has_attribute(ID::init))
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continue;
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// for (auto [cell, port] : ctx.outs) {
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// SigSpec sig = cell->getPort(port);
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// log_assert(sig.is_wire());
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// if (!sig.as_wire()->has_attribute(ID::init))
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// continue;
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Const init = sig.as_wire()->attributes.at(ID::init);
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sig.as_wire()->attributes.erase(ID::init);
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changed += sig.size();
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}
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// Const init = sig.as_wire()->attributes.at(ID::init);
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// sig.as_wire()->attributes.erase(ID::init);
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// changed += sig.size();
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// }
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log_cmd_error("Not implemented\n"); (void)mod;
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return changed;
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}
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@ -217,8 +224,6 @@ struct AbstractPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (mode != State)
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design->bufNormalize(true);
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unsigned int changed = 0;
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if ((mode == State) || (mode == Value)) {
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@ -249,8 +254,6 @@ struct AbstractPass : public Pass {
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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if (mode != State)
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design->bufNormalize(false);
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}
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} AbstractPass;
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