mirror of https://github.com/YosysHQ/yosys.git
abstract: -state refactor sigbit rep pool collection
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@ -43,10 +43,7 @@ bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, E
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return true;
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}
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unsigned int abstract_state(Module* mod, EnableLogic enable) {
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CellTypes ct;
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ct.setup_internals_ff();
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SigMap sigmap(mod);
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pool<SigBit> gather_selected_reps(Module* mod, SigMap& sigmap) {
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pool<SigBit> selected_representatives;
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// Collect reps for all wire bits of selected wires
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@ -60,6 +57,14 @@ unsigned int abstract_state(Module* mod, EnableLogic enable) {
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if (cell->output(conn.first))
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for (auto bit : conn.second.bits())
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selected_representatives.insert(sigmap(bit));
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return selected_representatives;
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}
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unsigned int abstract_state(Module* mod, EnableLogic enable) {
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CellTypes ct;
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ct.setup_internals_ff();
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SigMap sigmap(mod);
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pool<SigBit> selected_representatives = gather_selected_reps(mod, sigmap);
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unsigned int changed = 0;
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std::vector<FfData> ffs;
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