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Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger

This commit is contained in:
Eddie Hung 2019-02-12 09:21:46 -08:00
parent a2ae393811 04c580fde7
commit 6faad18874
1 changed files with 1 additions and 3 deletions
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4
frontends/aiger/aigerparse.cc
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@ -102,7 +102,6 @@ void AigerReader::parse_aiger()
if (f.peek() == '\n') if (f.peek() == '\n')
break; break;
// Else constraint (TODO) // Else constraint (TODO)
break;
} }
else else
log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
@ -225,7 +224,7 @@ void AigerReader::parse_aiger_ascii()
std::getline(f, line); // Ignore up to start of next line std::getline(f, line); // Ignore up to start of next line
// Parse AND // Parse AND
for (unsigned i = 0; i < A; ++i, ++line_count) { for (unsigned i = 0; i < A; ++i) {
if (!(f >> l1 >> l2 >> l3)) if (!(f >> l1 >> l2 >> l3))
log_error("Line %u cannot be interpreted as an AND!\n", line_count); log_error("Line %u cannot be interpreted as an AND!\n", line_count);
@ -236,7 +235,6 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
} }
std::getline(f, line); // Ignore up to start of next line
} }
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref) static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)