$size() seems to work now with or without the optional parameter.

Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.

frontends/ast/simplify.cc

@@ -1872,26 +1872,39 @@ skip_dynamic_range_lvalue_expansion:;
 
 			if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits"))
 			{
-				if (children.size() != 1)
+				if (str == "\\$bits" && children.size() != 1)
 					log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
 							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
 
+				if (str == "\\$size" && children.size() != 1 && children.size() != 2)
+					log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n",
+							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+
+				int dim = 1;
+				if (str == "\\$size" && children.size() == 2) {
+					AstNode *buf = children[1]->clone();
+					dim = buf->asInt(false);
+					delete buf;
+				}
 				AstNode *buf = children[0]->clone();
 				int mem_depth = 1;
 				AstNode *id_ast = NULL;
 				
+
 				// Is this needed?
 				//while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 				buf->detectSignWidth(width_hint, sign_hint);
-				if (str == "\\$bits") {
+				if (buf->type == AST_IDENTIFIER) {
-					if (buf->type == AST_IDENTIFIER) {
+					id_ast = buf->id2ast;
-						id_ast = buf->id2ast;
+					if (id_ast == NULL && current_scope.count(buf->str))
-						if (id_ast == NULL && current_scope.count(buf->str))
+						id_ast = current_scope.at(buf->str);
-							id_ast = current_scope.at(buf->str);
+					if (!id_ast)
-						if (!id_ast)
+						log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
-							log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+					if (id_ast->type == AST_MEMORY) {
-						if (id_ast->type == AST_MEMORY) {
+						// We got here only if the argument is a memory
-							AstNode *mem_range = id_ast->children[1];
+						// Otherwise $size() and $bits() return the expression width
+						AstNode *mem_range = id_ast->children[1];
+						if (str == "\\$bits") {
 							if (mem_range->type == AST_RANGE) {
 								if (!mem_range->range_valid)
 									log_error("Failed to detect width of memory access `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
@@ -1901,6 +1914,23 @@ skip_dynamic_range_lvalue_expansion:;
 									mem_depth *= (n->range_left - n->range_right + 1);
 							} else
 								log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
+						} else {
+							// $size()
+							if (mem_range->type == AST_RANGE) {
+								if (!mem_range->range_valid)
+									log_error("Failed to detect width of memory access `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
+								if (dim == 1)
+									width_hint = mem_range->range_left - mem_range->range_right + 1;
+							} else if (mem_range->type == AST_MULTIRANGE) {
+								log("multirange!\n");
+								int s = mem_range->children.size();
+								if (dim <= s) {
+									auto n = mem_range->children[dim-1]; 
+									width_hint = (n->range_left - n->range_right + 1);
+								} else if (dim > s+1)
+									log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, mem_range->str.c_str(), s+1, filename.c_str(), linenum);
+							} else
+								log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
 						}
 					}
 				}

tests/simple/functions01.sv

@@ -1,16 +1,26 @@
 module functions01;
 
 wire [3:0]x;
-wire [$size(x)-1:0]x_size;
-wire [$size({x, x})-1:0]xx_size;
 wire [3:0]y[0:5];
-wire [$size(y)-1:0]y_size;
 wire [3:0]z[0:5][0:7];
-wire [$size(z)-1:0]z_size;
 
-wire [$bits(x)-1:0]x_bits;
+//wire [$size(x)-1:0]x_size;
-wire [$bits({x, x})-1:0]xx_bits;
+//wire [$size({x, x})-1:0]xx_size;
-wire [$bits(y)-1:0]y_bits;
+//wire [$size(y)-1:0]y_size;
-wire [$bits(z)-1:0]z_bits;
+//wire [$size(z)-1:0]z_size;
+
+assert property ($size(x) == 4);
+assert property ($size({3{x}}) == 3*4);
+assert property ($size(y) == 6);
+assert property ($size(y, 1) == 6);
+assert property ($size(y, 2) == 4);
+
+//wire [$bits(x)-1:0]x_bits;
+//wire [$bits({x, x})-1:0]xx_bits;
+
+assert property ($bits(x) == 4);
+assert property ($bits(y) == 4*6);
+assert property ($bits(z) == 4*6*8);
+
 
 endmodule