mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3439 from YosysHQ/micko/filepath_improve
File path encoding improvements
This commit is contained in:
Miodrag Milanović
GitHub
commit
6b4dbf6c36
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@ -45,7 +45,7 @@ using namespace AST_INTERNAL;
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// helper function for creating RTLIL code for unary operations
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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return;
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}
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IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
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set_src_attr(cell, that);
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@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -138,7 +138,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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log_assert(cond.size() == 1);
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std::stringstream sstr;
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sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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sstr << "$ternary$" << RTLIL::encode_filename(that->filename) << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
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set_src_attr(cell, that);
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@ -321,7 +321,7 @@ struct AST_INTERNAL::ProcessGenerator
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LookaheadRewriter la_rewriter(always);
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// generate process and simple root case
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->filename).c_str(), always->location.first_line, autoidx++));
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set_src_attr(proc, always);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -1776,7 +1776,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_MEMRD:
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{
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std::stringstream sstr;
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sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
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set_src_attr(cell, this);
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@ -1814,7 +1814,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_MEMINIT:
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{
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std::stringstream sstr;
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sstr << "$meminit$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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SigSpec en_sig = children[2]->genRTLIL();
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@ -1869,7 +1869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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IdString cellname;
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if (str.empty())
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cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
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cellname = stringf("%s$%s:%d$%d", celltype.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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else
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cellname = str;
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@ -1240,7 +1240,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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// create the indirection wire
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std::stringstream sstr;
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sstr << "$indirect$" << ref->name.c_str() << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string tmp_str = sstr.str();
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add_wire_for_ref(ref, tmp_str);
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@ -2127,7 +2127,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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std::swap(data_range_left, data_range_right);
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std::stringstream sstr;
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sstr << "$mem2bits$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$mem2bits$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string wire_id = sstr.str();
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
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@ -2714,14 +2714,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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// mask and shift operations, disabled for now
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AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire_mask->is_logic = true;
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while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { }
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current_ast_mod->children.push_back(wire_mask);
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire_data->is_logic = true;
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while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
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@ -2732,7 +2732,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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shift_expr->detectSignWidth(shamt_width_hint, shamt_sign_hint);
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AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true)));
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wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire_sel->is_logic = true;
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wire_sel->is_signed = shamt_sign_hint;
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@ -2809,7 +2809,7 @@ skip_dynamic_range_lvalue_expansion:;
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if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL)
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{
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std::stringstream sstr;
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sstr << "$formal$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$formal$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
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AstNode *wire_check = new AstNode(AST_WIRE);
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@ -2918,7 +2918,7 @@ skip_dynamic_range_lvalue_expansion:;
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newNode = new AstNode(AST_BLOCK);
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AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true)));
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wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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current_ast_mod->children.push_back(wire_tmp);
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current_scope[wire_tmp->str] = wire_tmp;
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wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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@ -2956,7 +2956,7 @@ skip_dynamic_range_lvalue_expansion:;
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(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE)
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{
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std::stringstream sstr;
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sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
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int mem_width, mem_size, addr_bits;
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@ -3228,7 +3228,7 @@ skip_dynamic_range_lvalue_expansion:;
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AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
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mkconst_int(width_hint-1, true), mkconst_int(0, true)));
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reg->str = stringf("$past$%s:%d$%d$%d", filename.c_str(), location.first_line, myidx, i);
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reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, myidx, i);
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reg->is_reg = true;
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reg->is_signed = sign_hint;
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@ -3733,7 +3733,7 @@ skip_dynamic_range_lvalue_expansion:;
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std::stringstream sstr;
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sstr << str << "$func$" << filename << ":" << location.first_line << "$" << (autoidx++) << '.';
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sstr << str << "$func$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++) << '.';
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std::string prefix = sstr.str();
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AstNode *decl = current_scope[str];
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@ -4586,7 +4586,7 @@ static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> &
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if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) {
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AstNode *mem = that->id2ast;
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS))
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mem2reg_places[mem].insert(stringf("%s:%d", that->filename.c_str(), that->location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS;
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}
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}
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@ -4614,14 +4614,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
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// activate mem2reg if this is assigned in an async proc
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if (flags & AstNode::MEM2REG_FL_ASYNC) {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC;
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}
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// remember if this is assigned blocking (=)
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if (type == AST_ASSIGN_EQ) {
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if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
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proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
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}
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@ -4638,11 +4638,11 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
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// remember where this is
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if (flags & MEM2REG_FL_INIT) {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT;
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} else {
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if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE))
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE;
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}
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}
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@ -4656,7 +4656,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
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// flag if used after blocking assignment (in same proc)
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if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
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mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
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mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
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mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2;
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}
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}
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@ -4846,7 +4846,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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children[0]->children[0]->children[0]->type != AST_CONSTANT)
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{
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std::stringstream sstr;
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sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$mem2reg_wr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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int mem_width, mem_size, addr_bits;
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@ -4962,7 +4962,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
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else
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{
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std::stringstream sstr;
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sstr << "$mem2reg_rd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
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sstr << "$mem2reg_rd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
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std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
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int mem_width, mem_size, addr_bits;
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@ -183,7 +183,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
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{
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std::string s = stringf("$verific$%s", obj->Name());
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if (obj->Linefile())
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s += stringf("$%s:%d", Verific::LineFile::GetFileName(obj->Linefile()), Verific::LineFile::GetLineNo(obj->Linefile()));
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s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())).c_str(), Verific::LineFile::GetLineNo(obj->Linefile()));
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s += stringf("$%d", autoidx++);
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return s;
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}
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@ -2828,9 +2828,11 @@ struct VerificPass : public Pass {
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for (auto &ext : verific_libexts)
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veri_file::AddLibExt(ext.c_str());
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while (argidx < GetSize(args))
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file_names.Insert(args[argidx++].c_str());
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while (argidx < GetSize(args)) {
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std::string filename(args[argidx++]);
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rewrite_filename(filename);
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file_names.Insert(strdup(filename.c_str()));
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}
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if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
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verific_error_msg.clear();
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log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
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@ -2843,36 +2845,48 @@ struct VerificPass : public Pass {
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#ifdef VERIFIC_VHDL_SUPPORT
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if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
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for (argidx++; argidx < GetSize(args); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
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log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
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for (argidx++; argidx < GetSize(args); argidx++) {
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std::string filename(args[argidx]);
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rewrite_filename(filename);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87))
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log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str());
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}
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verific_import_pending = true;
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goto check_error;
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}
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if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
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vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
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for (argidx++; argidx < GetSize(args); argidx++)
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if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
|
||||
log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
|
||||
for (argidx++; argidx < GetSize(args); argidx++) {
|
||||
std::string filename(args[argidx]);
|
||||
rewrite_filename(filename);
|
||||
if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93))
|
||||
log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str());
|
||||
}
|
||||
verific_import_pending = true;
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
|
||||
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
|
||||
for (argidx++; argidx < GetSize(args); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
|
||||
log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
|
||||
for (argidx++; argidx < GetSize(args); argidx++) {
|
||||
std::string filename(args[argidx]);
|
||||
rewrite_filename(filename);
|
||||
if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K))
|
||||
log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str());
|
||||
}
|
||||
verific_import_pending = true;
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
|
||||
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
|
||||
for (argidx++; argidx < GetSize(args); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
|
||||
log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
|
||||
for (argidx++; argidx < GetSize(args); argidx++) {
|
||||
std::string filename(args[argidx]);
|
||||
rewrite_filename(filename);
|
||||
if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008))
|
||||
log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str());
|
||||
}
|
||||
verific_import_pending = true;
|
||||
goto check_error;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -440,6 +440,21 @@ namespace RTLIL
|
|||
}
|
||||
};
|
||||
|
||||
static inline std::string encode_filename(const std::string &filename)
|
||||
{
|
||||
std::stringstream val;
|
||||
if (!std::any_of(filename.begin(), filename.end(), [](char c) {
|
||||
return static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;
|
||||
})) return filename;
|
||||
for (unsigned char const c : filename) {
|
||||
if (c < 33 || c > 126)
|
||||
val << stringf("$%02x", c);
|
||||
else
|
||||
val << c;
|
||||
}
|
||||
return val.str();
|
||||
}
|
||||
|
||||
// see calc.cc for the implementation of this functions
|
||||
RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
||||
RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
|
|||
QbfSolutionType ret;
|
||||
const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
|
||||
const std::string smtbmc_warning = "z3: WARNING:";
|
||||
const std::string smtbmc_cmd = stringf("%s -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
|
||||
const std::string smtbmc_cmd = stringf("\"%s\" -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
|
||||
yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(),
|
||||
(opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(),
|
||||
(opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(),
|
||||
|
|
|
|||
|
|
@ -789,15 +789,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
|
||||
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
|
||||
|
||||
std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
|
||||
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
|
||||
|
||||
if (!liberty_files.empty() || !genlib_files.empty()) {
|
||||
for (std::string liberty_file : liberty_files)
|
||||
abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
|
||||
abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str());
|
||||
for (std::string liberty_file : genlib_files)
|
||||
abc_script += stringf("read_library %s; ", liberty_file.c_str());
|
||||
abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
|
||||
if (!constr_file.empty())
|
||||
abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
|
||||
abc_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
|
||||
} else
|
||||
if (!lut_costs.empty())
|
||||
abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
|
||||
|
|
@ -1085,7 +1085,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
fclose(f);
|
||||
}
|
||||
|
||||
buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
|
||||
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
|
||||
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
|
||||
|
||||
#ifndef YOSYS_LINK_ABC
|
||||
|
|
|
|||
|
|
@ -175,12 +175,12 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
|
|||
if (!lut_costs.empty())
|
||||
abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
|
||||
else if (!lut_file.empty())
|
||||
abc9_script += stringf("read_lut %s; ", lut_file.c_str());
|
||||
abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str());
|
||||
else
|
||||
log_abort();
|
||||
|
||||
log_assert(!box_file.empty());
|
||||
abc9_script += stringf("read_box %s; ", box_file.c_str());
|
||||
abc9_script += stringf("read_box \"%s\"; ", box_file.c_str());
|
||||
abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
|
||||
|
||||
if (!script_file.empty()) {
|
||||
|
|
@ -264,7 +264,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
|
|||
fclose(f);
|
||||
}
|
||||
|
||||
buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
|
||||
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
|
||||
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
|
||||
|
||||
#ifndef YOSYS_LINK_ABC
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
*.log
|
||||
*.json
|
||||
/run-test.mk
|
||||
+*_synth.v
|
||||
+*_testbench
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ generate_target() {
|
|||
generate_ys_test() {
|
||||
ys_file=$1
|
||||
yosys_args=${2:-}
|
||||
generate_target "$ys_file" "$YOSYS_BASEDIR/yosys -ql ${ys_file%.*}.log $yosys_args $ys_file"
|
||||
generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args $ys_file"
|
||||
}
|
||||
|
||||
# $ generate_bash_test bash_file
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#!/usr/bin/env bash
|
||||
|
||||
libs=""
|
||||
libs=()
|
||||
genvcd=false
|
||||
use_xsim=false
|
||||
use_modelsim=false
|
||||
|
|
@ -15,7 +15,7 @@ xinclude_opts=""
|
|||
minclude_opts=""
|
||||
scriptfiles=""
|
||||
scriptopt=""
|
||||
toolsdir="$(cd $(dirname $0); pwd)"
|
||||
toolsdir="$(cd "$(dirname "$0")"; pwd)"
|
||||
warn_iverilog_git=false
|
||||
# The following are used in verilog to firrtl regression tests.
|
||||
# Typically these will be passed as environment variables:
|
||||
|
|
@ -25,8 +25,8 @@ firrtl2verilog=""
|
|||
xfirrtl="../xfirrtl"
|
||||
abcprog="$toolsdir/../../yosys-abc"
|
||||
|
||||
if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
|
||||
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
|
||||
if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
|
||||
( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
|
||||
fi
|
||||
|
||||
while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
|
||||
|
|
@ -38,7 +38,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
|
|||
G)
|
||||
warn_iverilog_git=true ;;
|
||||
l)
|
||||
libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
|
||||
libs+=("$(cd "$(dirname "$OPTARG")"; pwd)/$(basename "$OPTARG")");;
|
||||
w)
|
||||
genvcd=true ;;
|
||||
k)
|
||||
|
|
@ -162,7 +162,7 @@ do
|
|||
cp ../${bn}_tb.v ${bn}_tb.v
|
||||
fi
|
||||
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
|
||||
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \
|
||||
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
|
||||
"$toolsdir"/../../techlibs/common/simlib.v \
|
||||
"$toolsdir"/../../techlibs/common/simcells.v
|
||||
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
|
||||
|
|
@ -171,11 +171,11 @@ do
|
|||
test_passes() {
|
||||
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
|
||||
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
|
||||
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
|
||||
${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
|
||||
"$toolsdir"/../../techlibs/common/simlib.v \
|
||||
"$toolsdir"/../../techlibs/common/simcells.v
|
||||
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
|
||||
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
|
||||
"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
|
||||
test_count=$(( test_count + 1 ))
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue