mirror of https://github.com/YosysHQ/yosys.git
cellmatch: Delegate evaluation to `ConstEval`
This commit is contained in:
Martin Povišer
Emil J. Tywoniak
parent
86e1080f05
commit
6a9858cdad
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@ -2,6 +2,7 @@
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/utils.h"
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#include <algorithm>
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@ -78,95 +79,48 @@ uint64_t p_class(int k, uint64_t lut)
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bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
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{
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SigMap sigmap(m);
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CellTypes ff_types;
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ff_types.setup_stdcells_mem();
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dict<SigBit, Cell*> driver;
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for (auto cell : m->selected_cells()) {
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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continue;
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for (auto cell : m->cells()) {
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if (ff_types.cell_known(cell->type)) {
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log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
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return false;
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}
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if (!cell->type.in(ID($_NOT_), ID($_AND_)))
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log_error("Unsupported cell in module '%s': %s of type %s\n",
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log_id(m), log_id(cell), log_id(cell->type));
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driver[sigmap(cell->getPort(ID::Y))] = cell;
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}
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TopoSort<Cell*> sort;
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for (auto cell : m->cells())
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if (cell->type.in(ID($_NOT_), ID($_AND_))) {
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sort.node(cell);
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SigSpec inputs = cell->type == ID($_AND_)
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? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)})
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: cell->getPort(ID::A);
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for (auto bit : sigmap(inputs))
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if (driver.count(bit))
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sort.edge(driver.at(bit), cell);
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}
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SigSpec inputs = module_inputs(m);
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SigSpec outputs = module_outputs(m);
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int ninputs = inputs.size(), noutputs = outputs.size();
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if (!sort.sort())
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log_error("Module %s contains combinational loops.\n", log_id(m));
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dict<SigBit, uint64_t> states;
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states[State::S0] = 0;
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states[State::S1] = ~(uint64_t) 1;
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{
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uint64_t sieves[6] = {
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0xaaaaaaaaaaaaaaaa,
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0xcccccccccccccccc,
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0xf0f0f0f0f0f0f0f0,
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0xff00ff00ff00ff00,
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0xffff0000ffff0000,
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0xffffffff00000000,
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};
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SigSpec inputs = sigmap(module_inputs(m));
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if (inputs.size() > 6) {
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if (ninputs > 6) {
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log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
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return false;
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}
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for (int i = 0; i < inputs.size(); i++)
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states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1);
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luts.clear();
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luts.resize(noutputs);
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ConstEval ceval(m);
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for (int i = 0; i < 1 << ninputs; i++) {
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ceval.clear();
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for (int j = 0; j < ninputs; j++)
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ceval.set(inputs[j], (i & (1 << j)) ? State::S1 : State::S0);
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for (int j = 0; j < noutputs; j++) {
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SigSpec bit = outputs[j];
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if (!ceval.eval(bit)) {
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log("Failed to evaluate output '%s' in module '%s'.\n",
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log_signal(outputs[j]), log_id(m));
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return false;
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}
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for (auto cell : sort.sorted) {
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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continue;
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log_assert(ceval.eval(bit));
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if (cell->type == ID($_AND_)) {
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SigSpec a = sigmap(cell->getPort(ID::A));
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SigSpec b = sigmap(cell->getPort(ID::B));
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if (!states.count(a) || !states.count(b))
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log_error("Cell %s in module %s sources an undriven wire!",
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log_id(cell), log_id(m));
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states[sigmap(cell->getPort(ID::Y))] = \
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states.at(a) & states.at(b);
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} else if (cell->type == ID($_NOT_)) {
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SigSpec a = sigmap(cell->getPort(ID::A));
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if (!states.count(a))
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log_error("Cell %s in module %s sources an undriven wire!",
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log_id(cell), log_id(m));
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states[sigmap(cell->getPort(ID::Y))] = ~states.at(a);
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} else {
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log_abort();
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if (bit[0] == State::S1)
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luts[j] |= 1 << i;
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}
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}
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for (auto bit : module_outputs(m)) {
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if (!states.count(sigmap(bit)))
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log_error("Output port %s in module %s is undriven!",
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log_signal(bit), log_id(m));
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luts.push_back(states.at(sigmap(bit)));
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}
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return true;
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}
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@ -184,10 +138,9 @@ struct CellmatchPass : Pass {
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log("former to instances of the latter. This techmap rule is saved in yet another\n");
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log("design called '$cellmatch_map', which is created if non-existent.\n");
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log("\n");
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log("This pass restricts itself to combinational modules which must be modeled with an\n");
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log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n");
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log("This pass restricts itself to combinational modules. Modules are functionally\n");
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log("equivalent as long as their truth tables are identical upto a permutation of\n");
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log("inputs and outputs. The number of inputs is limited to 6.\n");
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log("inputs and outputs. The supported number of inputs is limited to 6.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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