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sigmap(wire) should inherit port_output status of POs

This commit is contained in:
Eddie Hung 2019-11-22 16:46:26 -08:00
parent 2ef2e2c040
commit 6a52897aee
1 changed files with 19 additions and 1 deletions
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20
passes/hierarchy/submod.cc
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@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@ -32,6 +33,7 @@ struct SubmodWorker
CellTypes ct;
RTLIL::Design *design;
RTLIL::Module *module;
pool<Wire*> outputs;
bool copy_mode;
std::string opt_name;
@ -125,7 +127,7 @@ struct SubmodWorker
if (wire->port_input)
flags.is_ext_driven = true;
if (wire->port_output)
if (wire->port_output || outputs.count(wire))
flags.is_ext_used = true;
bool new_wire_port_input = false;
@ -219,6 +221,22 @@ struct SubmodWorker
ct.setup_stdcells_mem();
ct.setup_design(design);
SigMap sigmap(module);
for (auto port : module->ports) {
auto wire = module->wire(port);
if (!wire->port_output)
continue;
auto sig = sigmap(wire);
for (auto c : sig.chunks()) {
if (!c.wire)
continue;
if (c.wire == wire)
continue;
outputs.insert(c.wire);
log_dump(c.wire->name);
}
}
if (opt_name.empty())
{
for (auto &it : module->wires_)