mirror of https://github.com/YosysHQ/yosys.git
techmap: use +/techmap.v instead of an ad-hoc code generator.
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@ -1 +0,0 @@
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techmap.inc
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@ -45,18 +45,6 @@ OBJS += passes/techmap/flowmap.o
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OBJS += passes/techmap/extractinv.o
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OBJS += passes/techmap/extractinv.o
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endif
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endif
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GENFILES += passes/techmap/techmap.inc
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passes/techmap/techmap.inc: techlibs/common/techmap.v
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$(Q) mkdir -p $(dir $@)
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$(P) echo "// autogenerated from $<" > $@.new
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$(Q) echo "static char stdcells_code[] = {" >> $@.new
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$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
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$(Q) echo "0};" >> $@.new
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$(Q) mv $@.new $@
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passes/techmap/techmap.o: passes/techmap/techmap.inc
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ifeq ($(DISABLE_SPAWN),0)
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ifeq ($(DISABLE_SPAWN),0)
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TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE)
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TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE)
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EXTRA_OBJS += passes/techmap/filterlib.o
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EXTRA_OBJS += passes/techmap/filterlib.o
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@ -27,7 +27,6 @@
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#include <string.h>
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#include <string.h>
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#include "simplemap.h"
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#include "simplemap.h"
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#include "passes/techmap/techmap.inc"
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YOSYS_NAMESPACE_BEGIN
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YOSYS_NAMESPACE_BEGIN
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@ -1282,8 +1281,7 @@ struct TechmapPass : public Pass {
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RTLIL::Design *map = new RTLIL::Design;
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RTLIL::Design *map = new RTLIL::Design;
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if (map_files.empty()) {
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if (map_files.empty()) {
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std::istringstream f(stdcells_code);
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Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
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Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
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} else {
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} else {
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for (auto &fn : map_files)
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for (auto &fn : map_files)
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if (fn.compare(0, 1, "%") == 0) {
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if (fn.compare(0, 1, "%") == 0) {
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