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Don't track , ... contradictions through x/z-bits

This commit is contained in:
Clifford Wolf 2017-08-25 16:18:17 +02:00
parent db6d78a186
commit 68c42f3a19
1 changed files with 4 additions and 1 deletions
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5
passes/opt/opt_expr.cc
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@ -1277,7 +1277,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
{ {
SigBit bit_a = i < a_width ? assign_map(sig_a[i]) : State::S0; SigBit bit_a = i < a_width ? assign_map(sig_a[i]) : State::S0;
SigBit bit_b = i < b_width ? assign_map(sig_b[i]) : State::S0; SigBit bit_b = i < b_width ? assign_map(sig_b[i]) : State::S0;
contradiction_cache.merge(bit_a, bit_b);
if (bit_a != State::Sx && bit_a != State::Sz &&
bit_b != State::Sx && bit_b != State::Sz)
contradiction_cache.merge(bit_a, bit_b);
if (bit_b < bit_a) if (bit_b < bit_a)
std::swap(bit_a, bit_b); std::swap(bit_a, bit_b);