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more indent fix

This commit is contained in:
Chun Lin Min 2024-07-02 13:51:48 -07:00
parent 2ced2752e9
commit 68a11c9941
3 changed files with 25 additions and 25 deletions
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44
techlibs/mchp/LSRAM.txt
View File

@ -44,12 +44,12 @@ ram block $__LSRAM_TDP_ {
option "WIDTH_CONFIG" "REGULAR" {
# Data-Width | Address bits
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# Data-Width| Address bits
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# 14 address bits
abits 14;
@ -59,10 +59,10 @@ ram block $__LSRAM_TDP_ {
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width | Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# Data-Width| Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# Quick "hack" to fix address bit alignment by setting address bits to 12.
# If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
@ -133,13 +133,13 @@ ram block $__LSRAM_SDP_ {
option "WIDTH_CONFIG" "REGULAR" {
# Data-Width | Address bits
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# 32 | 9
# Data-Width| Address bits
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# 32 | 9
abits 14;
@ -151,11 +151,11 @@ ram block $__LSRAM_SDP_ {
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width | Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# 40 | 9
# Data-Width| Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# 40 | 9
# Same trick as TSP RAM for alignment
abits 12;

4
techlibs/mchp/LSRAM_map.v
View File

@ -68,8 +68,8 @@ assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_B_ADDR : {PORT_B_AD
// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)
parameter PORT_A_RD_USED = 0;
parameter PORT_A_WR_USED = 0;
wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
// wires for write data
generate

2
techlibs/mchp/uSRAM.txt
View File

@ -43,7 +43,7 @@ ram block $__uSRAM_AR_ {
# synchronous read
# NOTE: synchronous read can be realized by the address pipeline register or data pipeline register.
# This assumes address is synchronized
# This assumes address is synchronized
ram block $__uSRAM_SR_ {
cost 42;