quicklogic: Move pp3 tests one level down

Makefile

@@ -880,7 +880,7 @@ endif
 	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
-	+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh

tests/arch/quicklogic/pp3/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/add_sub.v
+read_verilog ../../common/add_sub.v
 hierarchy -top top
 equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

tests/arch/quicklogic/pp3/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/adffs.v
+read_verilog ../../common/adffs.v
 design -save read
 
 hierarchy -top adff

tests/arch/quicklogic/pp3/counter.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/counter.v
+read_verilog ../../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/quicklogic/pp3/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/dffs.v
+read_verilog ../../common/dffs.v
 rename dff my_dff # Work around conflicting module names between test and vendor cells
 rename dffe my_dffe
 design -save read

tests/arch/quicklogic/pp3/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/fsm.v
+read_verilog ../../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

tests/arch/quicklogic/pp3/latches.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/latches.v
+read_verilog ../../common/latches.v
 design -save read
 
 hierarchy -top latchp

tests/arch/quicklogic/pp3/logic.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/logic.v
+read_verilog ../../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check

tests/arch/quicklogic/pp3/mux.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/mux.v
+read_verilog ../../common/mux.v
 design -save read
 
 hierarchy -top mux2

tests/arch/quicklogic/pp3/run-test.sh

@@ -1,4 +1,4 @@
 #!/usr/bin/env bash
 set -eu
-source ../../gen-tests-makefile.sh
+source ../../../gen-tests-makefile.sh
 run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

tests/arch/quicklogic/pp3/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog ../common/tribuf.v
+read_verilog ../../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf