diff --git a/Makefile b/Makefile
index b980bfdd2..f467330c8 100644
--- a/Makefile
+++ b/Makefile
@@ -880,7 +880,7 @@ endif
 	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
-	+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh
diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/pp3/add_sub.ys
similarity index 93%
rename from tests/arch/quicklogic/add_sub.ys
rename to tests/arch/quicklogic/pp3/add_sub.ys
index 47db42afc..c5e9fb29b 100644
--- a/tests/arch/quicklogic/add_sub.ys
+++ b/tests/arch/quicklogic/pp3/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/add_sub.v
+read_verilog ../../common/add_sub.v
 hierarchy -top top
 equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/pp3/adffs.ys
similarity index 98%
rename from tests/arch/quicklogic/adffs.ys
rename to tests/arch/quicklogic/pp3/adffs.ys
index 43f36c20c..fb9f34df4 100644
--- a/tests/arch/quicklogic/adffs.ys
+++ b/tests/arch/quicklogic/pp3/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/adffs.v
+read_verilog ../../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/pp3/counter.ys
similarity index 95%
rename from tests/arch/quicklogic/counter.ys
rename to tests/arch/quicklogic/pp3/counter.ys
index 9a7dcdf08..5095cb8ef 100644
--- a/tests/arch/quicklogic/counter.ys
+++ b/tests/arch/quicklogic/pp3/counter.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/counter.v
+read_verilog ../../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/pp3/dffs.ys
similarity index 97%
rename from tests/arch/quicklogic/dffs.ys
rename to tests/arch/quicklogic/pp3/dffs.ys
index 2bcfbf672..f5023e48e 100644
--- a/tests/arch/quicklogic/dffs.ys
+++ b/tests/arch/quicklogic/pp3/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/dffs.v
+read_verilog ../../common/dffs.v
 rename dff my_dff # Work around conflicting module names between test and vendor cells
 rename dffe my_dffe
 design -save read
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/pp3/fsm.ys
similarity index 96%
rename from tests/arch/quicklogic/fsm.ys
rename to tests/arch/quicklogic/pp3/fsm.ys
index 50dcb71b1..418db8025 100644
--- a/tests/arch/quicklogic/fsm.ys
+++ b/tests/arch/quicklogic/pp3/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/fsm.v
+read_verilog ../../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/pp3/latches.ys
similarity index 96%
rename from tests/arch/quicklogic/latches.ys
rename to tests/arch/quicklogic/pp3/latches.ys
index bcef42990..90a4f515b 100644
--- a/tests/arch/quicklogic/latches.ys
+++ b/tests/arch/quicklogic/pp3/latches.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/latches.v
+read_verilog ../../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/pp3/logic.ys
similarity index 94%
rename from tests/arch/quicklogic/logic.ys
rename to tests/arch/quicklogic/pp3/logic.ys
index 9c34ddaeb..ecddda577 100644
--- a/tests/arch/quicklogic/logic.ys
+++ b/tests/arch/quicklogic/pp3/logic.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/logic.v
+read_verilog ../../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/pp3/mux.ys
similarity index 98%
rename from tests/arch/quicklogic/mux.ys
rename to tests/arch/quicklogic/pp3/mux.ys
index 5214bb787..a3b12a73d 100644
--- a/tests/arch/quicklogic/mux.ys
+++ b/tests/arch/quicklogic/pp3/mux.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/mux.v
+read_verilog ../../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/pp3/run-test.sh
similarity index 79%
rename from tests/arch/quicklogic/run-test.sh
rename to tests/arch/quicklogic/pp3/run-test.sh
index 4be4b70ae..3f8515f9a 100755
--- a/tests/arch/quicklogic/run-test.sh
+++ b/tests/arch/quicklogic/pp3/run-test.sh
@@ -1,4 +1,4 @@
 #!/usr/bin/env bash
 set -eu
-source ../../gen-tests-makefile.sh
+source ../../../gen-tests-makefile.sh
 run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/pp3/tribuf.ys
similarity index 93%
rename from tests/arch/quicklogic/tribuf.ys
rename to tests/arch/quicklogic/pp3/tribuf.ys
index d74fbbcdd..f68a0d779 100644
--- a/tests/arch/quicklogic/tribuf.ys
+++ b/tests/arch/quicklogic/pp3/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/tribuf.v
+read_verilog ../../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf