Added "submod -name ..." support

passes/submod/submod.cc

@@ -29,6 +29,7 @@ struct SubmodWorker
 	CellTypes ct;
 	RTLIL::Design *design;
 	RTLIL::Module *module;
+	std::string opt_name;
 
 	struct SubModule
 	{
@@ -188,9 +189,9 @@ struct SubmodWorker
 		module->cells[new_cell->name] = new_cell;
 	}
 
-	SubmodWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module)
+	SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, std::string opt_name = std::string()) : design(design), module(module), opt_name(opt_name)
 	{
-		if (!design->selected_whole_module(module->name))
+		if (!design->selected_whole_module(module->name) && opt_name.empty())
 			return;
 
 		if (module->processes.size() > 0) {
@@ -208,6 +209,8 @@ struct SubmodWorker
 		ct.setup_stdcells();
 		ct.setup_stdcells_mem();
 
+		if (opt_name.empty())
+		{
 			for (auto &it : module->wires)
 				it.second->attributes.erase("\\submod");
 
@@ -232,6 +235,22 @@ struct SubmodWorker
 
 				submodules[submod_str].cells.insert(cell);
 			}
+		}
+		else
+		{
+			for (auto &it : module->cells)
+			{
+				RTLIL::Cell *cell = it.second;
+				if (!design->selected(module, cell))
+					continue;
+				submodules[opt_name].name = opt_name;
+				submodules[opt_name].full_name = RTLIL::escape_id(opt_name);
+				submodules[opt_name].cells.insert(cell);
+			}
+
+			if (submodules.size() == 0)
+				log("Nothing selected -> do nothing.\n");
+		}
 
 		for (auto &it : submodules)
 			handle_submodule(it.second);
@@ -256,17 +275,36 @@ struct SubmodPass : public Pass {
 		log("This pass only operates on completely selected modules with no processes\n");
 		log("or memories.\n");
 		log("\n");
+		log("\n");
+		log("    submod -name <name> [selection]\n");
+		log("\n");
+		log("As above, but don't use the 'submod' attribute but instead use the selection.\n");
+		log("Only objects from one module might be selected. The value of the -name option\n");
+		log("is used as the value of the 'submod' attribute above.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n");
 		log_push();
 
+		std::string opt_name;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-name" && argidx+1 < args.size()) {
+				opt_name = args[++argidx];
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (opt_name.empty())
+		{
 			Pass::call(design, "opt_rmunused");
 			log_header("Continuing SUBMOD pass.\n");
 
-		extra_args(args, 1, design);
-
 			std::set<std::string> handled_modules;
 
 			bool did_something = true;
@@ -274,7 +312,7 @@ struct SubmodPass : public Pass {
 				did_something = false;
 				std::vector<std::string> queued_modules;
 				for (auto &mod_it : design->modules)
-				if (handled_modules.count(mod_it.first) == 0)
+					if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
 						queued_modules.push_back(mod_it.first);
 				for (auto &modname : queued_modules)
 					if (design->modules.count(modname) != 0) {
@@ -286,5 +324,23 @@ struct SubmodPass : public Pass {
 
 			Pass::call(design, "opt_rmunused");
 		}
+		else
+		{
+			RTLIL::Module *module = NULL;
+			for (auto &mod_it : design->modules) {
+				if (!design->selected_module(mod_it.first))
+					continue;
+				if (module != NULL)
+					log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod_it.first.c_str());
+				module = mod_it.second;
+			}
+			if (module == NULL)
+				log("Nothing selected -> do nothing.\n");
+			else
+				SubmodWorker worker(design, module, opt_name);
+		}
+
+		log_pop();
+	}
 } SubmodPass;