mirror of https://github.com/YosysHQ/yosys.git
add initial version of functional C++ backend
This commit is contained in:
Emily Schmidt
parent
dd5ec84a26
commit
63dea89fac
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OBJS += backends/functional/cxx.o
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/drivertools.h"
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#include "kernel/topo_scc.h"
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#include "kernel/functional.h"
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#include "kernel/graphtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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const char *reserved_keywords[] = {
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"alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit",
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"atomic_noexcept","auto","bitand","bitor","bool","break","case",
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"catch","char","char16_t","char32_t","char8_t","class","co_await",
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"co_return","co_yield","compl","concept","const","const_cast","consteval",
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"constexpr","constinit","continue","decltype","default","delete",
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"do","double","dynamic_cast","else","enum","explicit","export",
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"extern","false","float","for","friend","goto","if","inline",
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"int","long","mutable","namespace","new","noexcept","not","not_eq",
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"nullptr","operator","or","or_eq","private","protected","public",
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"reflexpr","register","reinterpret_cast","requires","return","short",
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"signed","sizeof","static","static_assert","static_cast","struct",
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"switch","synchronized","template","this","thread_local","throw",
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"true","try","typedef","typeid","typename","union","unsigned",
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"using","virtual","void","volatile","wchar_t","while","xor","xor_eq",
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nullptr
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};
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struct CxxScope {
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pool<std::string> used_names;
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dict<IdString, std::string> name_map;
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CxxScope() {
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for(const char **p = reserved_keywords; *p != nullptr; p++)
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reserve(*p);
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}
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void reserve(std::string name) {
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used_names.insert(name);
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}
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std::string insert(IdString id) {
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std::string str = RTLIL::unescape_id(id);
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for(size_t i = 0; i < str.size(); i++)
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if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i]))
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str[i] = '_';
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if(used_names.count(str) == 0){
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used_names.insert(str);
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name_map.insert({id, str});
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return str;
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}
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for (int idx = 0 ; ; idx++){
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std::string suffixed = str + "_" + std::to_string(idx);
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if (used_names.count(suffixed) == 0) {
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used_names.insert(suffixed);
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if(name_map.count(id) == 0)
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name_map.insert({id, suffixed});
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return suffixed;
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}
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}
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}
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std::string operator[](IdString id) {
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if(name_map.count(id) > 0)
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return name_map[id];
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else
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return insert(id);
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}
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};
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struct CxxWriter {
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std::ostream &f;
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CxxWriter(std::ostream &out) : f(out) {}
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void printf(const char *fmt, ...)
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{
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va_list va;
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va_start(va, fmt);
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f << vstringf(fmt, va);
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va_end(va);
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}
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};
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struct CxxStruct {
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std::string name;
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dict<IdString, std::string> types;
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CxxScope scope;
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CxxStruct(std::string name) : name(name) {
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scope.reserve("out");
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scope.reserve("dump");
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}
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void insert(IdString name, std::string type) {
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scope.insert(name);
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types.insert({name, type});
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}
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void print(CxxWriter &f) {
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f.printf("struct %s {\n", name.c_str());
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for (auto p : types) {
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f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
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}
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f.printf("\n\ttemplate <typename T> void dump(T &out) {\n");
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for (auto p : types) {
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f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str());
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}
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f.printf("\t}\n};\n\n");
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}
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std::string operator[](IdString field) {
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return scope[field];
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}
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};
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struct CxxFunction {
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IdString name;
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int width;
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dict<IdString, Const> parameters;
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CxxFunction(IdString name, int width) : name(name), width(width) {}
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CxxFunction(IdString name, int width, dict<IdString, Const> parameters) : name(name), width(width), parameters(parameters) {}
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bool operator==(CxxFunction const &other) const {
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return name == other.name && parameters == other.parameters && width == other.width;
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}
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unsigned int hash() const {
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return mkhash(name.hash(), parameters.hash());
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}
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};
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typedef ComputeGraph<CxxFunction, int, IdString, IdString> CxxComputeGraph;
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class CxxComputeGraphFactory {
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CxxComputeGraph &graph;
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using T = CxxComputeGraph::Ref;
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static bool is_single_output(IdString type)
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{
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auto it = yosys_celltypes.cell_types.find(type);
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return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
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}
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public:
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CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {}
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T slice(T a, int in_width, int offset, int out_width) {
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assert(offset + out_width <= in_width);
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return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array<T, 1>{a});
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}
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T extend(T a, int in_width, int out_width, bool is_signed) {
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assert(in_width < out_width);
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if(is_signed)
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return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
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else
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return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array<T, 1>{a});
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}
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T concat(T a, int a_width, T b, int b_width) {
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return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array<T, 2>{a, b});
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}
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T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array<T, 2>{a, b}); }
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T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array<T, 2>{a, b}); }
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T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array<T, 2>{a, b}); }
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T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array<T, 2>{a, b}); }
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T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array<T, 2>{a, b}); }
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T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array<T, 1>{a}); }
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T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array<T, 1>{a}); }
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T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array<T, 3>{a, b, s}); }
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T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array<T, 3>{a, b, s}); }
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T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array<T, 1>{a}); }
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T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array<T, 1>{a}); }
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T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array<T, 1>{a}); }
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T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array<T, 2>{a, b}); }
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T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array<T, 2>{a, b}); }
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T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array<T, 2>{a, b}); }
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T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array<T, 2>{a, b}); }
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T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array<T, 2>{a, b}); }
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T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array<T, 2>{a, b}); }
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T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
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T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
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T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
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T constant(RTLIL::Const value) {
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return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0);
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}
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T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); }
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T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); }
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T cell_output(T cell, IdString type, IdString name, int width) {
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if (is_single_output(type))
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return cell;
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else
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return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array<T, 1>{cell});
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}
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T multiple(vector<T> args, int width) {
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return graph.add(CxxFunction(ID($$multiple), width), 0, args);
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}
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T undriven(int width) {
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return graph.add(CxxFunction(ID($$undriven), width), 0);
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}
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T create_pending(int width) {
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return graph.add(CxxFunction(ID($$pending), width), 0);
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}
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void update_pending(T pending, T node) {
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assert(pending.function().name == ID($$pending));
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pending.set_function(CxxFunction(ID($$buf), pending.function().width));
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pending.append_arg(node);
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}
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void declare_output(T node, IdString name) {
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node.assign_key(name);
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}
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void declare_state(T node, IdString name) {
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node.assign_key(name);
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}
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void suggest_name(T node, IdString name) {
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node.sparse_attr() = name;
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}
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};
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struct FunctionalCxxBackend : public Backend
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{
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FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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}
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CxxComputeGraph calculate_compute_graph(RTLIL::Module *module)
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{
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CxxComputeGraph compute_graph;
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CxxComputeGraphFactory factory(compute_graph);
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ComputeGraphConstruction<CxxComputeGraph::Ref, CxxComputeGraphFactory> construction(factory);
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construction.add_module(module);
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construction.process_queue();
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// Perform topo sort and detect SCCs
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CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph);
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bool scc = false;
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std::vector<int> perm;
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topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) {
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perm.insert(perm.end(), begin, end);
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if (end > begin + 1)
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{
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log_warning("SCC:");
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for (int *i = begin; i != end; ++i)
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log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : "");
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log("\n");
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scc = true;
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}
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}, /* sources_first */ true);
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compute_graph.permute(perm);
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if(scc) log_error("combinational loops, aborting\n");
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// Forward $$buf
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std::vector<int> alias;
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perm.clear();
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for (int i = 0; i < compute_graph.size(); ++i)
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{
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auto node = compute_graph[i];
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if (node.function().name == ID($$buf) && node.arg(0).index() < i)
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{
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int target_index = alias[node.arg(0).index()];
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auto target_node = compute_graph[perm[target_index]];
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if(!target_node.has_sparse_attr() && node.has_sparse_attr())
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target_node.sparse_attr() = node.sparse_attr();
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alias.push_back(target_index);
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}
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else
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{
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alias.push_back(GetSize(perm));
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perm.push_back(i);
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}
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}
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compute_graph.permute(perm, alias);
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return compute_graph;
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}
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void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph)
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{
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dict<IdString, int> inputs, state;
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CxxWriter f(stream);
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// Dump the compute graph
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for (int i = 0; i < compute_graph.size(); ++i)
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{
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auto ref = compute_graph[i];
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if(ref.function().name == ID($$input))
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inputs[ref.function().parameters.begin()->first] = ref.function().width;
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if(ref.function().name == ID($$state))
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state[ref.function().parameters.begin()->first] = ref.function().width;
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}
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f.printf("#include \"sim.h\"\n");
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CxxStruct input_struct(name + "_Inputs");
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for (auto const &input : inputs)
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input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
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CxxStruct output_struct(name + "_Outputs");
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for (auto const &key : compute_graph.keys())
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if(state.count(key.first) == 0)
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output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">");
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CxxStruct state_struct(name + "_State");
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for (auto const &state_var : state)
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state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">");
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idict<std::string> node_names;
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CxxScope locals;
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input_struct.print(f);
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output_struct.print(f);
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state_struct.print(f);
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f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str());
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locals.reserve("input");
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locals.reserve("output");
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locals.reserve("current_state");
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locals.reserve("next_state");
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for (int i = 0; i < compute_graph.size(); ++i)
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{
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auto ref = compute_graph[i];
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int width = ref.function().width;
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std::string name;
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if(ref.has_sparse_attr())
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name = locals.insert(ref.sparse_attr());
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else
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name = locals.insert("\\n" + std::to_string(i));
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node_names(name);
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if(ref.function().name == ID($$input))
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f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
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else if(ref.function().name == ID($$state))
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f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
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else if(ref.function().name == ID($$buf))
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f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str());
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else if(ref.function().name == ID($$cell_output))
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f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
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else if(ref.function().name == ID($$const)){
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auto c = ref.function().parameters.begin()->second;
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if(c.size() <= 32){
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f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int());
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}else{
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f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int());
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while(c.size() > 32){
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c = c.extract(32, c.size() - 32);
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f.printf(", %#x", c.as_int());
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}
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f.printf("});\n");
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}
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}else if(ref.function().name == ID($$undriven))
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f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str());
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else if(ref.function().name == ID($$slice))
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f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
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else if(ref.function().name == ID($$concat)){
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f.printf("\tauto %s = concat(", name.c_str());
|
||||
for (int i = 0, end = ref.size(); i != end; ++i){
|
||||
if(i > 0)
|
||||
f.printf(", ");
|
||||
f.printf("%s", node_names[ref.arg(i).index()].c_str());
|
||||
}
|
||||
f.printf(");\n");
|
||||
}else{
|
||||
f.printf("\t");
|
||||
if(ref.function().width > 0)
|
||||
f.printf("Signal<%d>", ref.function().width);
|
||||
else
|
||||
f.printf("%s_Outputs", log_id(ref.function().name));
|
||||
f.printf(" %s = %s", name.c_str(), log_id(ref.function().name));
|
||||
if(ref.function().parameters.count(ID(WIDTH))){
|
||||
f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int());
|
||||
}
|
||||
f.printf("(");
|
||||
for (int i = 0, end = ref.size(); i != end; ++i)
|
||||
f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str());
|
||||
f.printf("); //");
|
||||
for (auto const ¶m : ref.function().parameters)
|
||||
{
|
||||
if (param.second.empty())
|
||||
f.printf("[%s]", log_id(param.first));
|
||||
else
|
||||
f.printf("[%s=%s]", log_id(param.first), log_const(param.second));
|
||||
}
|
||||
f.printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
for (auto const &key : compute_graph.keys())
|
||||
{
|
||||
f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str());
|
||||
}
|
||||
f.printf("}\n");
|
||||
}
|
||||
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing Functional C++ backend.\n");
|
||||
|
||||
size_t argidx = 1;
|
||||
extra_args(f, filename, args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
log("Dumping module `%s'.\n", module->name.c_str());
|
||||
auto compute_graph = calculate_compute_graph(module);
|
||||
printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph);
|
||||
}
|
||||
}
|
||||
} FunctionalCxxBackend;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SIM_H
|
||||
#define SIM_H
|
||||
|
||||
#include <array>
|
||||
|
||||
template<size_t n>
|
||||
using Signal = std::array<bool, n>;
|
||||
|
||||
template<size_t n, size_t m>
|
||||
Signal<n> slice(Signal<m> const& a, size_t offset)
|
||||
{
|
||||
Signal<n> ret;
|
||||
|
||||
std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin());
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $const(uint32_t val)
|
||||
{
|
||||
size_t i;
|
||||
Signal<n> ret;
|
||||
|
||||
for(i = 0; i < n; i++)
|
||||
if(i < 32)
|
||||
ret[i] = val & (1<<i);
|
||||
else
|
||||
ret[i] = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $const(std::initializer_list<uint32_t> vals)
|
||||
{
|
||||
size_t k, i;
|
||||
Signal<n> ret;
|
||||
|
||||
k = 0;
|
||||
for (auto val : vals) {
|
||||
for(i = 0; i < 32; i++)
|
||||
if(i + k < n)
|
||||
ret[i + k] = val & (1<<i);
|
||||
k += 32;
|
||||
}
|
||||
for(; k < n; k++)
|
||||
ret[k] = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
bool as_bool(Signal<n> sig)
|
||||
{
|
||||
for(int i = 0; i < n; i++)
|
||||
if(sig[i])
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
uint32_t as_int(Signal<n> sig)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
for(int i = 0; i < n; i++)
|
||||
if(sig[i] && i < 32)
|
||||
ret |= 1<<i;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $mux(Signal<n> const& a, Signal<n> const &b, Signal<1> const &s)
|
||||
{
|
||||
return s[0] ? b : a;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $not(Signal<n> const& a)
|
||||
{
|
||||
Signal<n> ret;
|
||||
for(size_t i = 0; i < n; i++)
|
||||
ret[i] = !a[i];
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $neg(Signal<n> const& a)
|
||||
{
|
||||
Signal<n> ret;
|
||||
bool carry = true;
|
||||
for(size_t i = 0; i < n; i++) {
|
||||
int r = !a[i] + carry;
|
||||
ret[i] = (r & 1) != 0;
|
||||
carry = (r >> 1) != 0;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $reduce_or(Signal<n> const& a)
|
||||
{
|
||||
return { as_bool(a) };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $reduce_and(Signal<n> const& a)
|
||||
{
|
||||
for(size_t i = 0; i < n; i++)
|
||||
if(!a[i])
|
||||
return { false };
|
||||
return { true };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $reduce_bool(Signal<n> const& a)
|
||||
{
|
||||
return { as_bool(a) };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $logic_and(Signal<n> const& a, Signal<n> const& b)
|
||||
{
|
||||
return { as_bool(a) && as_bool(b) };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $logic_or(Signal<n> const& a, Signal<n> const& b)
|
||||
{
|
||||
return { as_bool(a) || as_bool(b) };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $logic_not(Signal<n> const& a)
|
||||
{
|
||||
return { !as_bool(a) };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $add(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
Signal<n> ret;
|
||||
size_t i;
|
||||
int x = 0;
|
||||
for(i = 0; i < n; i++){
|
||||
x += (int)a[i] + (int)b[i];
|
||||
ret[i] = x & 1;
|
||||
x >>= 1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
template<size_t n>
|
||||
Signal<n> $sub(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
Signal<n> ret;
|
||||
int x = 1;
|
||||
for(size_t i = 0; i < n; i++){
|
||||
x += (int)a[i] + (int)!b[i];
|
||||
ret[i] = x & 1;
|
||||
x >>= 1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $uge(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
for(size_t i = n; i-- != 0; )
|
||||
if(a[i] != b[i])
|
||||
return { a[i] };
|
||||
return { true };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $ugt(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
for(size_t i = n; i-- != 0; )
|
||||
if(a[i] != b[i])
|
||||
return { a[i] };
|
||||
return { false };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $ge(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
if(a[n-1] != b[n-1])
|
||||
return { b[n-1] };
|
||||
return $uge(a, b);
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $gt(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
if(a[n-1] != b[n-1])
|
||||
return { b[n-1] };
|
||||
return $ugt(a, b);
|
||||
}
|
||||
|
||||
template<size_t n> Signal<1> $ule(Signal<n> const& a, Signal<n> const &b) { return $uge(b, a); }
|
||||
template<size_t n> Signal<1> $ult(Signal<n> const& a, Signal<n> const &b) { return $ugt(b, a); }
|
||||
template<size_t n> Signal<1> $le(Signal<n> const& a, Signal<n> const &b) { return $ge(b, a); }
|
||||
template<size_t n> Signal<1> $lt(Signal<n> const& a, Signal<n> const &b) { return $gt(b, a); }
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $and(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
Signal<n> ret;
|
||||
for(size_t i = 0; i < n; i++)
|
||||
ret[i] = a[i] && b[i];
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $or(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
Signal<n> ret;
|
||||
for(size_t i = 0; i < n; i++)
|
||||
ret[i] = a[i] || b[i];
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<n> $xor(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
Signal<n> ret;
|
||||
for(size_t i = 0; i < n; i++)
|
||||
ret[i] = a[i] != b[i];
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t na, size_t nb>
|
||||
Signal<n> $shl(Signal<na> const& a, Signal<nb> const &b)
|
||||
{
|
||||
if(nb >= sizeof(int) * 8 - 1)
|
||||
for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
|
||||
assert(!b[i]);
|
||||
size_t amount = as_int(b);
|
||||
Signal<n> ret = $const<n>(0);
|
||||
if(amount < n){
|
||||
if(amount + na > n)
|
||||
std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount);
|
||||
else
|
||||
std::copy(a.begin(), a.end(), ret.begin() + amount);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t nb>
|
||||
Signal<n> $shr(Signal<n> const& a, Signal<nb> const &b)
|
||||
{
|
||||
if(nb >= sizeof(int) * 8 - 1)
|
||||
for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
|
||||
assert(!b[i]);
|
||||
size_t amount = as_int(b);
|
||||
Signal<n> ret;
|
||||
for (size_t i = 0; i < n; i++) {
|
||||
if(i + amount < n)
|
||||
ret[i] = a[i + amount];
|
||||
else
|
||||
ret[i] = false;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t nb>
|
||||
Signal<n> $asr(Signal<n> const& a, Signal<nb> const &b)
|
||||
{
|
||||
if(nb >= sizeof(int) * 8 - 1)
|
||||
for(size_t i = sizeof(int) * 8 - 1; i < nb; i++)
|
||||
assert(!b[i]);
|
||||
size_t amount = as_int(b);
|
||||
Signal<n> ret;
|
||||
for (size_t i = 0; i < n; i++) {
|
||||
if(i + amount < n)
|
||||
ret[i] = a[i + amount];
|
||||
else
|
||||
ret[i] = a[n - 1];
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $eq(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
for(size_t i = 0; i < n; i++)
|
||||
if(a[i] != b[i])
|
||||
return { false };
|
||||
return { true };
|
||||
}
|
||||
|
||||
template<size_t n>
|
||||
Signal<1> $ne(Signal<n> const& a, Signal<n> const &b)
|
||||
{
|
||||
for(size_t i = 0; i < n; i++)
|
||||
if(a[i] != b[i])
|
||||
return { true };
|
||||
return { false };
|
||||
}
|
||||
|
||||
template<size_t n, size_t ns>
|
||||
Signal<n> $pmux(Signal<n> const& a, Signal<n*ns> const &b, Signal<ns> const &s)
|
||||
{
|
||||
bool found;
|
||||
Signal<n> ret;
|
||||
|
||||
found = false;
|
||||
ret = a;
|
||||
for(size_t i = 0; i < ns; i++){
|
||||
if(s[i]){
|
||||
if(found)
|
||||
return $const<n>(0);
|
||||
found = true;
|
||||
ret = slice<n>(b, n * i);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t m>
|
||||
Signal<n+m> concat(Signal<n> const& a, Signal<m> const& b)
|
||||
{
|
||||
Signal<n + m> ret;
|
||||
std::copy(a.begin(), a.end(), ret.begin());
|
||||
std::copy(b.begin(), b.end(), ret.begin() + n);
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t m>
|
||||
Signal<n> $zero_extend(Signal<m> const& a)
|
||||
{
|
||||
assert(n >= m);
|
||||
Signal<n> ret;
|
||||
std::copy(a.begin(), a.end(), ret.begin());
|
||||
for(size_t i = m; i < n; i++)
|
||||
ret[i] = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template<size_t n, size_t m>
|
||||
Signal<n> $sign_extend(Signal<m> const& a)
|
||||
{
|
||||
assert(n >= m);
|
||||
Signal<n> ret;
|
||||
std::copy(a.begin(), a.end(), ret.begin());
|
||||
for(size_t i = m; i < n; i++)
|
||||
ret[i] = a[m-1];
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef GRAPHTOOLS_H
|
||||
#define GRAPHTOOLS_H
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/drivertools.h"
|
||||
#include "kernel/functional.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
template <class T, class Factory>
|
||||
class CellSimplifier {
|
||||
Factory &factory;
|
||||
T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) {
|
||||
log_assert(y_width > 0);
|
||||
int new_width = sizeof(int) * 8 - __builtin_clz(y_width);
|
||||
if (b_width <= new_width) {
|
||||
reduced_b_width = b_width;
|
||||
return b;
|
||||
} else {
|
||||
reduced_b_width = new_width;
|
||||
T lower_b = factory.slice(b, b_width, 0, new_width);
|
||||
T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width);
|
||||
return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width);
|
||||
}
|
||||
}
|
||||
public:
|
||||
T reduce_or(T a, int width) {
|
||||
if (width == 1)
|
||||
return a;
|
||||
return factory.reduce_or(a, width);
|
||||
}
|
||||
T extend(T a, int in_width, int out_width, bool is_signed) {
|
||||
if(in_width == out_width)
|
||||
return a;
|
||||
if(in_width > out_width)
|
||||
return factory.slice(a, in_width, 0, out_width);
|
||||
return factory.extend(a, in_width, out_width, is_signed);
|
||||
}
|
||||
T logical_shift_left(T a, T b, int y_width, int b_width) {
|
||||
int reduced_b_width;
|
||||
T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
|
||||
return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width);
|
||||
}
|
||||
T logical_shift_right(T a, T b, int y_width, int b_width) {
|
||||
int reduced_b_width;
|
||||
T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
|
||||
return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width);
|
||||
}
|
||||
T arithmetic_shift_right(T a, T b, int y_width, int b_width) {
|
||||
int reduced_b_width;
|
||||
T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
|
||||
return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width);
|
||||
}
|
||||
CellSimplifier(Factory &f) : factory(f) {}
|
||||
T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
|
||||
{
|
||||
int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
|
||||
int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
|
||||
int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int();
|
||||
bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool();
|
||||
bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool();
|
||||
if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){
|
||||
bool is_signed = a_signed && b_signed;
|
||||
T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed);
|
||||
T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed);
|
||||
if(cellType == ID($add))
|
||||
return factory.add(a, b, y_width);
|
||||
else if(cellType == ID($sub))
|
||||
return factory.sub(a, b, y_width);
|
||||
else if(cellType == ID($and))
|
||||
return factory.bitwise_and(a, b, y_width);
|
||||
else if(cellType == ID($or))
|
||||
return factory.bitwise_or(a, b, y_width);
|
||||
else if(cellType == ID($xor))
|
||||
return factory.bitwise_xor(a, b, y_width);
|
||||
else if(cellType == ID($xnor))
|
||||
return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width);
|
||||
else
|
||||
log_abort();
|
||||
}else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){
|
||||
bool is_signed = a_signed && b_signed;
|
||||
int width = max(a_width, b_width);
|
||||
T a = extend(inputs.at(ID(A)), a_width, width, is_signed);
|
||||
T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
|
||||
if(cellType.in({ID($eq), ID($eqx)}))
|
||||
return extend(factory.eq(a, b, width), 1, y_width, false);
|
||||
if(cellType.in({ID($ne), ID($nex)}))
|
||||
return extend(factory.ne(a, b, width), 1, y_width, false);
|
||||
else if(cellType == ID($lt))
|
||||
return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false);
|
||||
else if(cellType == ID($le))
|
||||
return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false);
|
||||
else if(cellType == ID($gt))
|
||||
return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false);
|
||||
else if(cellType == ID($ge))
|
||||
return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false);
|
||||
else
|
||||
log_abort();
|
||||
}else if(cellType.in({ID($logic_or), ID($logic_and)})){
|
||||
T a = reduce_or(inputs.at(ID(A)), a_width);
|
||||
T b = reduce_or(inputs.at(ID(B)), b_width);
|
||||
T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1);
|
||||
return extend(y, 1, y_width, false);
|
||||
}else if(cellType == ID($not)){
|
||||
T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
|
||||
return factory.bitwise_not(a, y_width);
|
||||
}else if(cellType == ID($pos)){
|
||||
return extend(inputs.at(ID(A)), a_width, y_width, a_signed);
|
||||
}else if(cellType == ID($neg)){
|
||||
T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
|
||||
return factory.neg(a, y_width);
|
||||
}else if(cellType == ID($logic_not)){
|
||||
T a = reduce_or(inputs.at(ID(A)), a_width);
|
||||
T y = factory.bitwise_not(a, 1);
|
||||
return extend(y, 1, y_width, false);
|
||||
}else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){
|
||||
T a = reduce_or(inputs.at(ID(A)), a_width);
|
||||
return extend(a, 1, y_width, false);
|
||||
}else if(cellType == ID($reduce_and)){
|
||||
T a = factory.reduce_and(inputs.at(ID(A)), a_width);
|
||||
return extend(a, 1, y_width, false);
|
||||
}else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){
|
||||
T a = factory.reduce_xor(inputs.at(ID(A)), a_width);
|
||||
T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a;
|
||||
return extend(y, 1, y_width, false);
|
||||
}else if(cellType == ID($shl) || cellType == ID($sshl)){
|
||||
T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed);
|
||||
T b = inputs.at(ID(B));
|
||||
return logical_shift_left(a, b, y_width, b_width);
|
||||
}else if(cellType == ID($shr) || cellType == ID($sshr)){
|
||||
int width = max(a_width, y_width);
|
||||
T a = extend(inputs.at(ID(A)), a_width, width, a_signed);
|
||||
T b = inputs.at(ID(B));
|
||||
T y = a_signed && cellType == ID($sshr) ?
|
||||
arithmetic_shift_right(a, b, width, b_width) :
|
||||
logical_shift_right(a, b, width, b_width);
|
||||
return extend(y, width, y_width, a_signed);
|
||||
}else if(cellType == ID($shiftx) || cellType == ID($shift)){
|
||||
int width = max(a_width, y_width);
|
||||
T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed);
|
||||
T b = inputs.at(ID(B));
|
||||
T shr = logical_shift_right(a, b, width, b_width);
|
||||
if(b_signed) {
|
||||
T sign_b = factory.slice(b, b_width, b_width - 1, 1);
|
||||
T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width);
|
||||
T y = factory.mux(shr, shl, sign_b, width);
|
||||
return extend(y, width, y_width, false);
|
||||
} else {
|
||||
return extend(shr, width, y_width, false);
|
||||
}
|
||||
}else if(cellType == ID($mux)){
|
||||
int width = parameters.at(ID(WIDTH)).as_int();
|
||||
return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width);
|
||||
}else if(cellType == ID($pmux)){
|
||||
int width = parameters.at(ID(WIDTH)).as_int();
|
||||
int s_width = parameters.at(ID(S_WIDTH)).as_int();
|
||||
return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width);
|
||||
}else if(cellType == ID($concat)){
|
||||
T a = inputs.at(ID(A));
|
||||
T b = inputs.at(ID(B));
|
||||
return factory.concat(a, a_width, b, b_width);
|
||||
}else if(cellType == ID($slice)){
|
||||
int offset = parameters.at(ID(OFFSET)).as_int();
|
||||
T a = inputs.at(ID(A));
|
||||
return factory.slice(a, a_width, offset, y_width);
|
||||
}else{
|
||||
log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
template <class T, class Factory>
|
||||
class ComputeGraphConstruction {
|
||||
std::deque<DriveSpec> queue;
|
||||
dict<DriveSpec, T> graph_nodes;
|
||||
idict<Cell *> cells;
|
||||
DriverMap driver_map;
|
||||
Factory& factory;
|
||||
CellSimplifier<T, Factory> simplifier;
|
||||
|
||||
T enqueue(DriveSpec const &spec)
|
||||
{
|
||||
auto it = graph_nodes.find(spec);
|
||||
if(it == graph_nodes.end()){
|
||||
auto node = factory.create_pending(spec.size());
|
||||
graph_nodes.insert({spec, node});
|
||||
queue.emplace_back(spec);
|
||||
return node;
|
||||
}else
|
||||
return it->second;
|
||||
}
|
||||
public:
|
||||
ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {}
|
||||
void add_module(Module *module)
|
||||
{
|
||||
driver_map.add(module);
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
|
||||
enqueue(DriveBitMarker(cells(cell), 0));
|
||||
}
|
||||
for (auto wire : module->wires()) {
|
||||
if (wire->port_output) {
|
||||
T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)));
|
||||
factory.declare_output(node, wire->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
void process_queue()
|
||||
{
|
||||
for (; !queue.empty(); queue.pop_front()) {
|
||||
DriveSpec spec = queue.front();
|
||||
T pending = graph_nodes.at(spec);
|
||||
|
||||
if (spec.chunks().size() > 1) {
|
||||
auto chunks = spec.chunks();
|
||||
T node = enqueue(chunks[0]);
|
||||
int width = chunks[0].size();
|
||||
for(size_t i = 1; i < chunks.size(); i++) {
|
||||
node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size());
|
||||
width += chunks[i].size();
|
||||
}
|
||||
factory.update_pending(pending, node);
|
||||
} else if (spec.chunks().size() == 1) {
|
||||
DriveChunk chunk = spec.chunks()[0];
|
||||
if (chunk.is_wire()) {
|
||||
DriveChunkWire wire_chunk = chunk.wire();
|
||||
if (wire_chunk.is_whole()) {
|
||||
if (wire_chunk.wire->port_input) {
|
||||
T node = factory.input(wire_chunk.wire->name, wire_chunk.width);
|
||||
factory.suggest_name(node, wire_chunk.wire->name);
|
||||
factory.update_pending(pending, node);
|
||||
} else {
|
||||
DriveSpec driver = driver_map(DriveSpec(wire_chunk));
|
||||
T node = enqueue(driver);
|
||||
factory.suggest_name(node, wire_chunk.wire->name);
|
||||
factory.update_pending(pending, node);
|
||||
}
|
||||
} else {
|
||||
DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width);
|
||||
T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width);
|
||||
factory.update_pending(pending, node);
|
||||
}
|
||||
} else if (chunk.is_port()) {
|
||||
DriveChunkPort port_chunk = chunk.port();
|
||||
if (port_chunk.is_whole()) {
|
||||
if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) {
|
||||
if (port_chunk.cell->type.in(ID($dff), ID($ff)))
|
||||
{
|
||||
Cell *cell = port_chunk.cell;
|
||||
T node = factory.state(cell->name, port_chunk.width);
|
||||
factory.suggest_name(node, port_chunk.cell->name);
|
||||
factory.update_pending(pending, node);
|
||||
for (auto const &conn : cell->connections()) {
|
||||
if (driver_map.celltypes.cell_input(cell->type, conn.first)) {
|
||||
T node = enqueue(DriveChunkPort(cell, conn));
|
||||
factory.declare_state(node, cell->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
|
||||
factory.suggest_name(cell, port_chunk.cell->name);
|
||||
T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
|
||||
factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str());
|
||||
factory.update_pending(pending, node);
|
||||
}
|
||||
} else {
|
||||
DriveSpec driver = driver_map(DriveSpec(port_chunk));
|
||||
factory.update_pending(pending, enqueue(driver));
|
||||
}
|
||||
} else {
|
||||
DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port)));
|
||||
T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width);
|
||||
factory.update_pending(pending, node);
|
||||
}
|
||||
} else if (chunk.is_constant()) {
|
||||
T node = factory.constant(chunk.constant());
|
||||
factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string());
|
||||
factory.update_pending(pending, node);
|
||||
} else if (chunk.is_multiple()) {
|
||||
vector<T> args;
|
||||
for (auto const &driver : chunk.multiple().multiple())
|
||||
args.push_back(enqueue(driver));
|
||||
T node = factory.multiple(args, chunk.size());
|
||||
factory.update_pending(pending, node);
|
||||
} else if (chunk.is_marker()) {
|
||||
Cell *cell = cells[chunk.marker().marker];
|
||||
dict<IdString, T> connections;
|
||||
for(auto const &conn : cell->connections()) {
|
||||
if(driver_map.celltypes.cell_input(cell->type, conn.first))
|
||||
connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
|
||||
}
|
||||
T node = simplifier.handle(cell->type, cell->parameters, connections);
|
||||
factory.update_pending(pending, node);
|
||||
} else if (chunk.is_none()) {
|
||||
T node = factory.undriven(chunk.size());
|
||||
factory.update_pending(pending, node);
|
||||
} else {
|
||||
log_error("unhandled drivespec: %s\n", log_signal(chunk));
|
||||
log_abort();
|
||||
}
|
||||
} else {
|
||||
log_abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue