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Remove write_verilog call

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Eddie Hung 2019-04-16 13:24:54 -07:00
parent aece97024d
commit 61ca83e099
1 changed files with 1 additions and 1 deletions
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2
backends/aiger/xaiger.cc
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@ -630,7 +630,7 @@ struct XAigerWriter
RTLIL::Selection& sel = holes_module->design->selection_stack.back(); RTLIL::Selection& sel = holes_module->design->selection_stack.back();
sel.select(holes_module); sel.select(holes_module);
Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v"); Pass::call(holes_module->design, "flatten; aigmap");
holes_module->design->selection_stack.pop_back(); holes_module->design->selection_stack.pop_back();