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Update codebase for macc_v2

This commit is contained in:
Martin Povišer 2025-01-10 13:42:26 +01:00
parent 5882055899
commit 61450e8b6e
9 changed files with 16 additions and 15 deletions
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2
docs/source/cell/word_arith.rst
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@ -1,7 +1,7 @@
Coarse arithmetics Coarse arithmetics
------------------ ------------------
.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells. .. todo:: Add information about `$alu`, `$fa`, `$macc_v2`, and `$lcu` cells.
The `$macc` cell type represents a generalized multiply and accumulate The `$macc` cell type represents a generalized multiply and accumulate
operation. The cell is purely combinational. It outputs the result of summing up operation. The cell is purely combinational. It outputs the result of summing up

2
docs/source/code_examples/fifo/fifo.ys
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@ -67,7 +67,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdat
# ======================================================== # ========================================================
alumacc alumacc
select -set new_cells t:$alu t:$macc select -set new_cells t:$alu t:$macc_v2
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
# ======================================================== # ========================================================

2
docs/source/getting_started/example_synth.rst
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@ -523,7 +523,7 @@ That brings us to the fourth and final part for the iCE40 synthesis flow:
:name: synth_coarse4 :name: synth_coarse4
Where before each type of arithmetic operation had its own cell, e.g. `$add`, we Where before each type of arithmetic operation had its own cell, e.g. `$add`, we
now want to extract these into `$alu` and `$macc` cells which can help identify now want to extract these into `$alu` and `$macc_v2` cells which can help identify
opportunities for reusing logic. We do this by running `alumacc`, which we can opportunities for reusing logic. We do this by running `alumacc`, which we can
see produce the following changes in our example design: see produce the following changes in our example design:

2
kernel/celledges.cc
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@ -453,7 +453,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
} }
// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
// FIXME: $lut $sop $alu $lcu $macc $fa // FIXME: $lut $sop $alu $lcu $macc $macc_v2 $fa
// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx // FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux // FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux

1
kernel/celltypes.h
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@ -144,6 +144,7 @@ struct CellTypes
setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true); setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true); setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true); setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
} }

2
kernel/consteval.h
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@ -310,7 +310,7 @@ struct ConstEval
} }
} }
} }
else if (cell->type == ID($macc)) else if (cell->type.in(ID($macc), ID($macc_v2)))
{ {
Macc macc; Macc macc;
macc.from_cell(cell); macc.from_cell(cell);

16
kernel/rtlil.cc
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@ -1472,16 +1472,16 @@ namespace {
error(__LINE__); error(__LINE__);
if (param(ID::NADDENDS) <= 0) if (param(ID::NADDENDS) <= 0)
error(__LINE__); error(__LINE__);
param_bits(ID::PRODUCT_NEGATED, param(ID::NPRODUCTS)); param_bits(ID::PRODUCT_NEGATED, min(param(ID::NPRODUCTS), 1));
param_bits(ID::ADDEND_NEGATED, param(ID::NADDENDS)); param_bits(ID::ADDEND_NEGATED, min(param(ID::NADDENDS), 1));
param_bits(ID::A_SIGNED, param(ID::NPRODUCTS)); param_bits(ID::A_SIGNED, min(param(ID::NPRODUCTS), 1));
param_bits(ID::B_SIGNED, param(ID::NPRODUCTS)); param_bits(ID::B_SIGNED, min(param(ID::NPRODUCTS), 1));
param_bits(ID::C_SIGNED, param(ID::NADDENDS)); param_bits(ID::C_SIGNED, min(param(ID::NADDENDS), 1));
if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED)) if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
error(__LINE__); error(__LINE__);
param_bits(ID::A_WIDTHS, param(ID::NPRODUCTS) * 16); param_bits(ID::A_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
param_bits(ID::B_WIDTHS, param(ID::NPRODUCTS) * 16); param_bits(ID::B_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
param_bits(ID::C_WIDTHS, param(ID::NADDENDS) * 16); param_bits(ID::C_WIDTHS, min(param(ID::NADDENDS) * 16, 1));
const Const &a_width = cell->getParam(ID::A_WIDTHS); const Const &a_width = cell->getParam(ID::A_WIDTHS);
const Const &b_width = cell->getParam(ID::B_WIDTHS); const Const &b_width = cell->getParam(ID::B_WIDTHS);
const Const &c_width = cell->getParam(ID::C_WIDTHS); const Const &c_width = cell->getParam(ID::C_WIDTHS);

2
kernel/satgen.cc
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@ -740,7 +740,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
return true; return true;
} }
if (cell->type == ID($macc)) if (cell->type.in(ID($macc), ID($macc_v2)))
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);

2
passes/techmap/booth.cc
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@ -218,7 +218,7 @@ struct BoothPassWorker {
log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool()); log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
is_signed = cell->getParam(ID::A_SIGNED).as_bool(); is_signed = cell->getParam(ID::A_SIGNED).as_bool();
} else if (cell->type == ID($macc)) { } else if (cell->type.in(ID($macc), ID($macc_v2))) {
Macc macc; Macc macc;
macc.from_cell(cell); macc.from_cell(cell);