diff --git a/docs/source/cell/word_arith.rst b/docs/source/cell/word_arith.rst
index 49070814a..8e3daa27f 100644
--- a/docs/source/cell/word_arith.rst
+++ b/docs/source/cell/word_arith.rst
@@ -1,7 +1,7 @@
 Coarse arithmetics
 ------------------
 
-.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
+.. todo:: Add information about `$alu`, `$fa`, `$macc_v2`, and `$lcu` cells.
 
 The `$macc` cell type represents a generalized multiply and accumulate
 operation. The cell is purely combinational. It outputs the result of summing up
diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys
index 57a28e63e..e6b9bf69d 100644
--- a/docs/source/code_examples/fifo/fifo.ys
+++ b/docs/source/code_examples/fifo/fifo.ys
@@ -67,7 +67,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdat
 # ========================================================
 
 alumacc
-select -set new_cells t:$alu t:$macc
+select -set new_cells t:$alu t:$macc_v2
 show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
 
 # ========================================================
diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst
index 189eaddfa..e215586cc 100644
--- a/docs/source/getting_started/example_synth.rst
+++ b/docs/source/getting_started/example_synth.rst
@@ -523,7 +523,7 @@ That brings us to the fourth and final part for the iCE40 synthesis flow:
    :name: synth_coarse4
 
 Where before each type of arithmetic operation had its own cell, e.g. `$add`, we
-now want to extract these into `$alu` and `$macc` cells which can help identify
+now want to extract these into `$alu` and `$macc_v2` cells which can help identify
 opportunities for reusing logic.  We do this by running `alumacc`, which we can
 see produce the following changes in our example design:
 
diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index bad7124d9..95f160612 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -453,7 +453,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 	}
 
 	// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
-	// FIXME: $lut $sop $alu $lcu $macc $fa
+	// FIXME: $lut $sop $alu $lcu $macc $macc_v2 $fa
 	// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
 	// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
 
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 3167a9add..0ce5db54d 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -144,6 +144,7 @@ struct CellTypes
 
 		setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
 		setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
+		setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);
 		setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
 	}
 
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 331d8f128..05e94ab86 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -310,7 +310,7 @@ struct ConstEval
 				}
 			}
 		}
-		else if (cell->type == ID($macc))
+		else if (cell->type.in(ID($macc), ID($macc_v2)))
 		{
 			Macc macc;
 			macc.from_cell(cell);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f2f36ba30..29a7ebf3e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1472,16 +1472,16 @@ namespace {
 					error(__LINE__);
 				if (param(ID::NADDENDS) <= 0)
 					error(__LINE__);
-				param_bits(ID::PRODUCT_NEGATED, param(ID::NPRODUCTS));
-				param_bits(ID::ADDEND_NEGATED, param(ID::NADDENDS));
-				param_bits(ID::A_SIGNED, param(ID::NPRODUCTS));
-				param_bits(ID::B_SIGNED, param(ID::NPRODUCTS));
-				param_bits(ID::C_SIGNED, param(ID::NADDENDS));
+				param_bits(ID::PRODUCT_NEGATED, min(param(ID::NPRODUCTS), 1));
+				param_bits(ID::ADDEND_NEGATED, min(param(ID::NADDENDS), 1));
+				param_bits(ID::A_SIGNED, min(param(ID::NPRODUCTS), 1));
+				param_bits(ID::B_SIGNED, min(param(ID::NPRODUCTS), 1));
+				param_bits(ID::C_SIGNED, min(param(ID::NADDENDS), 1));
 				if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
 					error(__LINE__);
-				param_bits(ID::A_WIDTHS, param(ID::NPRODUCTS) * 16);
-				param_bits(ID::B_WIDTHS, param(ID::NPRODUCTS) * 16);
-				param_bits(ID::C_WIDTHS, param(ID::NADDENDS) * 16);
+				param_bits(ID::A_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
+				param_bits(ID::B_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
+				param_bits(ID::C_WIDTHS, min(param(ID::NADDENDS) * 16, 1));
 				const Const &a_width = cell->getParam(ID::A_WIDTHS);
 				const Const &b_width = cell->getParam(ID::B_WIDTHS);
 				const Const &c_width = cell->getParam(ID::C_WIDTHS);
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index dd15b51f3..9e5fa9111 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -740,7 +740,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($macc))
+	if (cell->type.in(ID($macc), ID($macc_v2)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc
index dce7da486..cd9012e6c 100644
--- a/passes/techmap/booth.cc
+++ b/passes/techmap/booth.cc
@@ -218,7 +218,7 @@ struct BoothPassWorker {
 
 				log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
 				is_signed = cell->getParam(ID::A_SIGNED).as_bool();
-			} else if (cell->type == ID($macc)) {
+			} else if (cell->type.in(ID($macc), ID($macc_v2))) {
 				Macc macc;
 				macc.from_cell(cell);