riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix for python 2.6.6

This commit is contained in:
Clifford Wolf 2015-03-20 09:10:02 +01:00
parent aed4d763cf
commit 604c097f98
3 changed files with 172 additions and 165 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tests/fsm/generate.py
View File

@ -34,7 +34,8 @@ def random_expr(variables):
raise AssertionError raise AssertionError
for idx in range(50): for idx in range(50):
with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
rst2 = random.choice([False, True]) rst2 = random.choice([False, True])
if rst2: if rst2:
print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx))
@ -89,7 +90,8 @@ for idx in range(50):
print(' end') print(' end')
print(' end') print(' end')
print('endmodule') print('endmodule')
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
if test_verific: if test_verific:
print('read_verilog temp/uut_%05d.v' % idx) print('read_verilog temp/uut_%05d.v' % idx)
print('proc;; rename uut_%05d gold' % idx) print('proc;; rename uut_%05d gold' % idx)

9
tests/realmath/generate.py
View File

@ -40,7 +40,8 @@ def random_expression(depth = 3, maxparam = 0):
raise raise
for idx in range(100): for idx in range(100):
with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
for i in range(30): for i in range(30):
if idx < 10: if idx < 10:
@ -55,11 +56,13 @@ for idx in range(100):
for i in range(100): for i in range(100):
print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60)))
print('endmodule') print('endmodule')
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
print('read_verilog uut_%05d.v' % idx) print('read_verilog uut_%05d.v' % idx)
print('rename uut_%05d uut_%05d_syn' % (idx, idx)) print('rename uut_%05d uut_%05d_syn' % (idx, idx))
print('write_verilog uut_%05d_syn.v' % idx) print('write_verilog uut_%05d_syn.v' % idx)
with file('temp/uut_%05d_tb.v' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d_tb.v' % idx, 'w') as f:
with redirect_stdout(f):
print('module uut_%05d_tb;\n' % idx) print('module uut_%05d_tb;\n' % idx)
print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)])))
print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)])))

6
tests/share/generate.py
View File

@ -25,7 +25,8 @@ def maybe_plus_x(expr):
return expr return expr
for idx in range(100): for idx in range(100):
with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
if random.choice(['bin', 'uni']) == 'bin': if random.choice(['bin', 'uni']) == 'bin':
print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
op = random.choice([ op = random.choice([
@ -59,7 +60,8 @@ for idx in range(100):
random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
random_plus_x() if random.randint(0, 4) == 0 else '')) random_plus_x() if random.randint(0, 4) == 0 else ''))
print('endmodule') print('endmodule')
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): with file('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
print('read_verilog temp/uut_%05d.v' % idx) print('read_verilog temp/uut_%05d.v' % idx)
print('proc;;') print('proc;;')
print('copy uut_%05d gold' % idx) print('copy uut_%05d gold' % idx)