mirror of https://github.com/YosysHQ/yosys.git
extract_counter: Fix clock enable
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12fa4a3121
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@ -509,13 +509,15 @@ void counter_worker(
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cell->setPort(ID(CE), extract.ce);
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}
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else
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{
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cell->setParam(ID(HAS_CE), RTLIL::Const(0));
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cell->setPort(ID(CE), RTLIL::Const(1));
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}
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//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
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cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
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cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
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cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
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cell->setPort(ID(CE), RTLIL::Const(1));
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cell->setPort(ID(UP), RTLIL::Const(0));
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//Hook up any parallel outputs
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